{"id":2223634,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223634/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415202027.83008-3-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260415202027.83008-3-philmd@linaro.org>","date":"2026-04-15T20:20:22","name":"[RFC,v5,2/6] target/mips: Convert MSA LD/ST.B (Byte Vector)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f76e6407d392011fdfe7e04c63bf9c6c0cef4855","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.1/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415202027.83008-3-philmd@linaro.org/mbox/","series":[{"id":500037,"url":"http://patchwork.ozlabs.org/api/1.1/series/500037/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500037","date":"2026-04-15T20:20:20","name":"target/mips: Translate MSA vector load/store opcodes","version":5,"mbox":"http://patchwork.ozlabs.org/series/500037/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223634/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223634/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=QEG68PCb;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::435;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Replace runtime helpers by translation.\n\nReplace the legacy cpu_ld/st*_data_ra() calls by\ntcg_gen_qemu_ld/st() which allow to respect atomicity.\n\nConsider the host endianness.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/mips/tcg/msa_helper.h.inc | 1 -\n target/mips/tcg/msa_helper.c | 28 ----------------------------\n target/mips/tcg/msa_translate.c | 30 ++++++++++++++++++++++++------\n 3 files changed, 24 insertions(+), 35 deletions(-)","diff":"diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc\nindex 4963d1553a0..50a2732e916 100644\n--- a/target/mips/tcg/msa_helper.h.inc\n+++ b/target/mips/tcg/msa_helper.h.inc\n@@ -436,7 +436,6 @@ DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)\n #define MSALDST_PROTO(type) \\\n DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \\\n DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)\n-MSALDST_PROTO(b)\n MSALDST_PROTO(h)\n MSALDST_PROTO(w)\n MSALDST_PROTO(d)\ndiff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c\nindex f554b3d10ee..d9f35fca657 100644\n--- a/target/mips/tcg/msa_helper.c\n+++ b/target/mips/tcg/msa_helper.c\n@@ -8223,20 +8223,6 @@ static inline uint64_t bswap32x2(uint64_t x)\n return ror64(bswap64(x), 32);\n }\n \n-void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- /* Load 8 bytes at a time. Vector element ordering makes this LE. */\n- d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);\n- d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);\n- pwd->d[0] = d0;\n- pwd->d[1] = d1;\n-}\n-\n void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,\n target_ulong addr)\n {\n@@ -8310,20 +8296,6 @@ static inline void ensure_writable_pages(CPUMIPSState *env,\n }\n }\n \n-void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- int mmu_idx = mips_env_mmu_index(env);\n- uintptr_t ra = GETPC();\n-\n- ensure_writable_pages(env, addr, mmu_idx, ra);\n-\n- /* Store 8 bytes at a time. Vector element ordering makes this LE. */\n- cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra);\n- cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra);\n-}\n-\n void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,\n target_ulong addr)\n {\ndiff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c\nindex 2e1a769e032..340a0a14aaf 100644\n--- a/target/mips/tcg/msa_translate.c\n+++ b/target/mips/tcg/msa_translate.c\n@@ -756,8 +756,16 @@ TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df);\n \n static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n {\n+ static const MemOp mo_atom_df[4] = {\n+ MO_ATOM_NONE,\n+ };\n TCGv_i32 wd;\n+ TCGv_i128 t16;\n TCGv_va addr;\n+ MemOp mop;\n+ int idx = a->wd << 1;\n+ TCGv_i64 d0 = msa_wr_d[idx + FP_ENDIAN_IDX];\n+ TCGv_i64 d1 = msa_wr_d[idx + !FP_ENDIAN_IDX];\n \n if (!check_msa_enabled(ctx)) {\n return true;\n@@ -770,9 +778,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n \n if (is_load) {\n switch (a->df) {\n- case 0:\n- gen_helper_msa_ld_b(tcg_env, wd, addr);\n- return true;\n case 1:\n gen_helper_msa_ld_h(tcg_env, wd, addr);\n return true;\n@@ -785,9 +790,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n }\n } else {\n switch (a->df) {\n- case 0:\n- gen_helper_msa_st_b(tcg_env, wd, addr);\n- return true;\n case 1:\n gen_helper_msa_st_h(tcg_env, wd, addr);\n return true;\n@@ -800,6 +802,22 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n }\n }\n \n+ t16 = tcg_temp_new_i128();\n+\n+ mop = MO_128 | MO_LE;\n+ mop |= a->df << MO_ASHIFT; /* MO_ALIGN */\n+ mop |= mo_atom_df[a->df];\n+\n+ if (is_load) {\n+ tcg_gen_qemu_ld_i128(t16, addr, ctx->mem_idx, mop);\n+ tcg_gen_extr_i128_i64(d0, d1, t16);\n+ }\n+\n+ if (!is_load) {\n+ tcg_gen_concat_i64_i128(t16, d0, d1);\n+ tcg_gen_qemu_st_i128(t16, addr, ctx->mem_idx, mop);\n+ }\n+\n return true;\n }\n \n","prefixes":["RFC","v5","2/6"]}