{"id":2223210,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223210/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-10@git.sr.ht/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<177618728515.4917.14466194789826252277-10@git.sr.ht>","date":"2026-04-07T09:47:17","name":"[qemu,v3,10/10] ot_uart: switch from clock driven transmission to reg R/W driven transmission","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7e81b2a9ced6c9208404156dc47fefc42ccf013a","submitter":{"id":92675,"url":"http://patchwork.ozlabs.org/api/1.1/people/92675/?format=json","name":"~lexbaileylowrisc","email":"lexbaileylowrisc@git.sr.ht"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-10@git.sr.ht/mbox/","series":[{"id":499878,"url":"http://patchwork.ozlabs.org/api/1.1/series/499878/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499878","date":"2026-04-14T17:21:25","name":"Update opentitan uart (part of supporting opentitan version 1)","version":3,"mbox":"http://patchwork.ozlabs.org/series/499878/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223210/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223210/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" header.d=git.sr.ht\n header.i=@git.sr.ht header.a=rsa-sha256 header.s=20240113 header.b=TfH4BRea;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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bh=9Kniq8FRhqulospfv3oew3dMKhVcy/wDzgbPCpJAV3k=;\n c=simple/simple; d=git.sr.ht;\n h=From:Date:Subject:Reply-to:In-Reply-To:To:Cc; q=dns/txt; s=20240113;\n t=1776187286; v=1;\n b=TfH4BReaEuw7JvG36OdP/16JYcvxw9FhXFOyDe9P/t+rqvTapO3kdlScz8/CIwHXgopSHEif\n 8O5igK7UfTmdvrXW29rnHpvWrAODittNo1wY9FpjpeQWfyxzAqKiP270pujNWTeXN0XRO+acppu\n TWLokM6I0AX7SdvcG0trDvp57bWZJHL14W7Pd9HyFGxL6ENbu6G8qMwrMrLiQBNt0xKcmtJvOam\n V8PwbH7dC2AlD+Cj9gKhm2KRxUU8mFERrt9orjNPhEa0ywkyC10EMgjHmy3aKSs9hMFmpYXuy0P\n qgkKDQKjeRmCUOoXVt1BcO6/7Ov24fpuslGEvRXGDb2SQ==","From":"~lexbaileylowrisc ","Date":"Tue, 07 Apr 2026 10:47:17 +0100","Subject":"[PATCH qemu v3 10/10] ot_uart: switch from clock driven transmission\n to reg R/W driven transmission","Message-ID":"<177618728515.4917.14466194789826252277-10@git.sr.ht>","X-Mailer":"git.sr.ht","In-Reply-To":"<177618728515.4917.14466194789826252277-0@git.sr.ht>","To":"qemu-riscv@nongnu.org, Alistair Francis ","Cc":"Paolo Bonzini ,\n =?utf-8?q?Marc-Andr=C3=A9?= Lureau ,\n Palmer Dabbelt , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , qemu-devel@nongnu.org,\n qemu-riscv@nongnu.org, Amit Kumar-Hermosillo ,\n nabihestefan ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Received-SPF":"pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht;\n helo=mail-a.sr.ht","X-Spam_score_int":"17","X-Spam_score":"1.7","X-Spam_bar":"+","X-Spam_report":"(1.7 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405,\n DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"~lexbaileylowrisc ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Lex Bailey \n\nthis commit removes the need for the timer by instead transmitting from the TX\nfifo any time it has data in it and it is enabled. This case can only arise\nfrom a write to one of the registers in the UART, so the device will still work\nfully without the timer.\n\nSigned-off-by: Lex Bailey \n---\n hw/char/ot_uart.c | 91 ++++++++++++++++-----------------------\n hw/char/trace-events | 2 +-\n include/hw/char/ot_uart.h | 15 ++-----\n 3 files changed, 40 insertions(+), 68 deletions(-)","diff":"diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c\nindex 910bef00f2..af0cf9ee1a 100644\n--- a/hw/char/ot_uart.c\n+++ b/hw/char/ot_uart.c\n@@ -20,9 +20,10 @@\n #include \"qemu/osdep.h\"\n #include \"hw/char/ot_uart.h\"\n #include \"qemu/fifo8.h\"\n+#include \"qapi/error.h\"\n+#include \"chardev/char-fe.h\"\n #include \"hw/core/cpu.h\"\n #include \"hw/core/irq.h\"\n-#include \"hw/core/qdev-clock.h\"\n #include \"hw/core/qdev-properties.h\"\n #include \"hw/core/qdev-properties-system.h\"\n #include \"hw/core/registerfields.h\"\n@@ -152,6 +153,18 @@ static bool ot_uart_is_rx_enabled(const OtUARTState *s)\n return FIELD_EX32(s->regs[R_CTRL], CTRL, RX);\n }\n \n+static void ot_uart_check_baudrate(const OtUARTState *s)\n+{\n+ uint32_t nco = FIELD_EX32(s->regs[R_CTRL], CTRL, NCO);\n+\n+ unsigned baudrate = (unsigned)(((uint64_t)nco * (uint64_t)s->pclk) >>\n+ (R_CTRL_NCO_LENGTH + 4));\n+\n+ if (baudrate) {\n+ trace_ot_uart_check_baudrate(s->ot_id, s->pclk, baudrate);\n+ }\n+}\n+\n static int ot_uart_can_receive(void *opaque)\n {\n OtUARTState *s = opaque;\n@@ -284,7 +297,6 @@ static void ot_uart_xmit(OtUARTState *s)\n \n static void uart_write_tx_fifo(OtUARTState *s, uint8_t val)\n {\n- uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);\n if (fifo8_is_full(&s->tx_fifo)) {\n qemu_log_mask(LOG_GUEST_ERROR, \"ot_uart: TX FIFO overflow\");\n return;\n@@ -305,9 +317,6 @@ static void uart_write_tx_fifo(OtUARTState *s, uint8_t val)\n if (ot_uart_is_tx_enabled(s)) {\n ot_uart_xmit(s);\n }\n-\n- timer_mod(s->fifo_trigger_handle, current_time +\n- (s->char_tx_time * 4));\n }\n \n static void ot_uart_reset_enter(Object *obj, ResetType type)\n@@ -328,11 +337,6 @@ static void ot_uart_reset_enter(Object *obj, ResetType type)\n ot_uart_reset_tx_fifo(s);\n ot_uart_reset_rx_fifo(s);\n \n- s->tx_level = 0;\n- s->rx_level = 0;\n-\n- s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;\n-\n /*\n * do not reset `s->in_break`, as that tracks whether we are currently\n * receiving a break condition over UART RX from some device talking\n@@ -399,19 +403,16 @@ static gboolean ot_uart_watch_cb(void *do_not_use, GIOCondition cond,\n return FALSE;\n }\n \n-static uint64_t ot_uart_get_baud(OtUARTState *s)\n+static void ot_uart_clock_input(void *opaque, int irq, int level)\n {\n- uint64_t baud;\n+ OtUARTState *s = opaque;\n \n- baud = ((s->regs[R_CTRL] & R_CTRL_NCO_MASK) >> 16);\n- baud *= clock_get_hz(s->f_clk);\n- baud >>= 20;\n+ g_assert(irq == 0);\n \n- if (baud) {\n- trace_ot_uart_check_baudrate(s->ot_id, baud);\n- }\n+ s->pclk = (unsigned)level;\n \n- return baud;\n+ /* TODO: disable UART transfer when PCLK is 0 */\n+ ot_uart_check_baudrate(s);\n }\n \n static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n@@ -553,8 +554,6 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n /* This will also set an IRQ once the alert handler is added */\n break;\n case R_CTRL:\n- s->regs[R_CTRL] = value;\n-\n if (value & R_CTRL_NF_MASK) {\n qemu_log_mask(LOG_UNIMP,\n \"%s: UART_CTRL_NF is not supported\\n\", __func__);\n@@ -577,10 +576,19 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n qemu_log_mask(LOG_UNIMP,\n \"%s: UART_CTRL_RXBLVL is not supported\\n\", __func__);\n }\n- if (value & R_CTRL_NCO_MASK) {\n- uint64_t baud = ot_uart_get_baud(s);\n-\n- s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;\n+ uint32_t prev = s->regs[R_CTRL];\n+ s->regs[R_CTRL] = value & CTRL_MASK;\n+ uint32_t change = prev ^ s->regs[R_CTRL];\n+ if (change & R_CTRL_NCO_MASK) {\n+ ot_uart_check_baudrate(s);\n+ }\n+ if ((change & R_CTRL_RX_MASK) && ot_uart_is_rx_enabled(s) &&\n+ !ot_uart_is_sys_loopack_enabled(s)) {\n+ qemu_chr_fe_accept_input(&s->chr);\n+ }\n+ if ((change & R_CTRL_TX_MASK) && ot_uart_is_tx_enabled(s)) {\n+ /* try sending pending data from TX FIFO if any */\n+ ot_uart_xmit(s);\n }\n break;\n case R_WDATA:\n@@ -628,25 +636,6 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n }\n }\n \n-static void ot_uart_clk_update(void *opaque, ClockEvent event)\n-{\n- OtUARTState *s = opaque;\n-\n- /* recompute uart's speed on clock change */\n- uint64_t baud = ot_uart_get_baud(s);\n-\n- s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;\n-}\n-\n-static void fifo_trigger_update(void *opaque)\n-{\n- OtUARTState *s = opaque;\n-\n- if (s->regs[R_CTRL] & R_CTRL_TX_MASK) {\n- ot_uart_xmit(s);\n- }\n-}\n-\n static const MemoryRegionOps ot_uart_ops = {\n .read = ot_uart_read,\n .write = ot_uart_write,\n@@ -665,15 +654,12 @@ static int ot_uart_post_load(void *opaque, int version_id)\n \n static const VMStateDescription vmstate_ot_uart = {\n .name = TYPE_OT_UART,\n- .version_id = 2,\n- .minimum_version_id = 2,\n+ .version_id = 3,\n+ .minimum_version_id = 3,\n .post_load = ot_uart_post_load,\n .fields = (const VMStateField[]) {\n VMSTATE_STRUCT(tx_fifo, OtUARTState, 1, vmstate_fifo8, Fifo8),\n VMSTATE_STRUCT(rx_fifo, OtUARTState, 1, vmstate_fifo8, Fifo8),\n- VMSTATE_UINT32(tx_level, OtUARTState),\n- VMSTATE_UINT64(char_tx_time, OtUARTState),\n- VMSTATE_TIMER_PTR(fifo_trigger_handle, OtUARTState),\n VMSTATE_ARRAY(regs, OtUARTState, REGS_COUNT, 1, vmstate_info_uint32,\n uint32_t),\n VMSTATE_END_OF_LIST()\n@@ -708,10 +694,6 @@ static void ot_uart_init(Object *obj)\n {\n OtUARTState *s = OT_UART(obj);\n \n- s->f_clk = qdev_init_clock_in(DEVICE(obj), \"f_clock\",\n- ot_uart_clk_update, s, ClockUpdate);\n- clock_set_hz(s->f_clk, OT_UART_CLOCK);\n-\n for (unsigned index = 0; index < OT_UART_IRQ_NUM; index++) {\n sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irqs[index]);\n }\n@@ -735,8 +717,7 @@ static void ot_uart_realize(DeviceState *dev, Error **errp)\n \n g_assert(s->ot_id);\n \n- s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,\n- fifo_trigger_update, s);\n+ qdev_init_gpio_in_named(DEVICE(s), &ot_uart_clock_input, \"clock-in\", 1);\n \n fifo8_create(&s->tx_fifo, OT_UART_TX_FIFO_SIZE);\n fifo8_create(&s->rx_fifo, OT_UART_RX_FIFO_SIZE);\ndiff --git a/hw/char/trace-events b/hw/char/trace-events\nindex 17cc9ad2d5..c859d8af4e 100644\n--- a/hw/char/trace-events\n+++ b/hw/char/trace-events\n@@ -143,7 +143,7 @@ htif_uart_write_to_host(uint8_t device, uint8_t cmd, uint64_t payload) \"device:\n htif_uart_unknown_device_command(uint8_t device, uint8_t cmd, uint64_t payload) \"device: %u cmd: %02u payload: %016\" PRIx64\n \n # ot_uart.c\n-ot_uart_check_baudrate(const char *id, unsigned baud) \"%s: %u bps\"\n+ot_uart_check_baudrate(const char *id, unsigned pclk, unsigned baud) \"%s: @ %u Hz: %u bps\"\n ot_uart_connect_input_clock(const char *id, const char * srcname) \"%s: %s\"\n ot_uart_debug(const char *id, const char *msg) \"%s: %s\"\n ot_uart_io_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) \"%s: addr=0x%02x (%s), val=0x%x, pc=0x%x\"\ndiff --git a/include/hw/char/ot_uart.h b/include/hw/char/ot_uart.h\nindex 2f538e1f6f..7c2b5f3457 100644\n--- a/include/hw/char/ot_uart.h\n+++ b/include/hw/char/ot_uart.h\n@@ -23,11 +23,8 @@\n #include \"hw/core/sysbus.h\"\n #include \"qemu/fifo8.h\"\n #include \"chardev/char-fe.h\"\n-#include \"qemu/timer.h\"\n #include \"qom/object.h\"\n \n-#define OT_UART_CLOCK 50000000 /* 50MHz clock */\n-\n #define TYPE_OT_UART \"ot-uart\"\n OBJECT_DECLARE_TYPE(OtUARTState, OtUARTClass, OT_UART)\n \n@@ -39,13 +36,6 @@ struct OtUARTState {\n MemoryRegion mmio;\n qemu_irq irqs[9];\n \n- uint32_t tx_level;\n-\n- uint32_t rx_level;\n-\n- QEMUTimer *fifo_trigger_handle;\n- uint64_t char_tx_time;\n-\n uint32_t regs[13]; /* Length must be updated if regs added or removed */\n \n Fifo8 tx_fifo;\n@@ -53,10 +43,11 @@ struct OtUARTState {\n uint32_t tx_watermark_level;\n bool in_break;\n guint watch_tag;\n+ unsigned pclk; /* Current input clock */\n+ const char *clock_src_name; /* IRQ name once connected */\n \n char *ot_id;\n- Clock *f_clk;\n-\n+ DeviceState *clock_src;\n CharFrontend chr;\n bool oversample_break; /* Should mock break in the oversampled VAL reg? */\n bool toggle_break; /* Are incoming breaks temporary or toggled? */\n","prefixes":["qemu","v3","10/10"]}