{"id":2223206,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223206/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-9@git.sr.ht/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<177618728515.4917.14466194789826252277-9@git.sr.ht>","date":"2026-04-07T14:03:54","name":"[qemu,v3,09/10] ot_uart: add tracing","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4e5dd9ef39cdc095044568ca2ed6ea761d48487e","submitter":{"id":92675,"url":"http://patchwork.ozlabs.org/api/1.1/people/92675/?format=json","name":"~lexbaileylowrisc","email":"lexbaileylowrisc@git.sr.ht"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-9@git.sr.ht/mbox/","series":[{"id":499878,"url":"http://patchwork.ozlabs.org/api/1.1/series/499878/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499878","date":"2026-04-14T17:21:25","name":"Update opentitan uart (part of supporting opentitan version 1)","version":3,"mbox":"http://patchwork.ozlabs.org/series/499878/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223206/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223206/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" header.d=git.sr.ht\n header.i=@git.sr.ht header.a=rsa-sha256 header.s=20240113 header.b=b9MLvEGn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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bh=KLpuStIUCtdEwm7bU4ULI48OBxTw38QY1td1/B8iSN4=;\n c=simple/simple; d=git.sr.ht;\n h=From:Date:Subject:Reply-to:In-Reply-To:To:Cc; q=dns/txt; s=20240113;\n t=1776187286; v=1;\n b=b9MLvEGndhNeWJrtb/X660IC5s7kKSBsc2VnKodQ/wVhadUZe72jwJsPuYr6AWA5pnkcHpq1\n LXgEcNv2MTtLdA9jE7zs2RYyY7KBvP3hs4jQ+c01wojqWJ+qzL1s6sH916/cRn8fp2CdTFuWrTw\n VY14E2+SxDb38VB07pRoz0HU8zZDt7iWZ1d1boclAuB+6w5lbG+wnVwTyVOTNea8CtQFiBBnRxG\n /kTAc4LTlqYrsOP6eGYTm+JeYPAvhZycYQmnZUPXal09Ye/mpFHrqcNP2vbnn+SGAEGxCQ+o66c\n ecAqnDZK/rHbRErVDsoW7GmntUbn95PK3CAoKVc0gxuTg==","From":"~lexbaileylowrisc ","Date":"Tue, 07 Apr 2026 15:03:54 +0100","Subject":"[PATCH qemu v3 09/10] ot_uart: add tracing","Message-ID":"<177618728515.4917.14466194789826252277-9@git.sr.ht>","X-Mailer":"git.sr.ht","In-Reply-To":"<177618728515.4917.14466194789826252277-0@git.sr.ht>","To":"qemu-riscv@nongnu.org, Alistair Francis ","Cc":"Paolo Bonzini ,\n =?utf-8?q?Marc-Andr=C3=A9?= Lureau ,\n Palmer Dabbelt , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , qemu-devel@nongnu.org,\n qemu-riscv@nongnu.org, Amit Kumar-Hermosillo ,\n nabihestefan ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Received-SPF":"pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht;\n helo=mail-a.sr.ht","X-Spam_score_int":"17","X-Spam_score":"1.7","X-Spam_bar":"+","X-Spam_report":"(1.7 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405,\n DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"~lexbaileylowrisc ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Lex Bailey \n\nAdded some tracing to the OpenTitan UART for transparency when debugging\n\nSigned-off-by: Lex Bailey \n---\n hw/char/ot_uart.c | 19 +++++++++++++++++++\n hw/char/trace-events | 8 ++++++++\n hw/riscv/opentitan.c | 1 +\n include/hw/char/ot_uart.h | 1 +\n 4 files changed, 29 insertions(+)","diff":"diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c\nindex d00f7bee66..910bef00f2 100644\n--- a/hw/char/ot_uart.c\n+++ b/hw/char/ot_uart.c\n@@ -20,6 +20,7 @@\n #include \"qemu/osdep.h\"\n #include \"hw/char/ot_uart.h\"\n #include \"qemu/fifo8.h\"\n+#include \"hw/core/cpu.h\"\n #include \"hw/core/irq.h\"\n #include \"hw/core/qdev-clock.h\"\n #include \"hw/core/qdev-properties.h\"\n@@ -28,6 +29,7 @@\n #include \"migration/vmstate.h\"\n #include \"qemu/log.h\"\n #include \"qemu/module.h\"\n+#include \"trace.h\"\n \n REG32(INTR_STATE, 0x00)\n SHARED_FIELD(INTR_TX_WATERMARK, 0, 1)\n@@ -126,6 +128,9 @@ static void ot_uart_update_irqs(OtUARTState *s)\n {\n uint32_t state_masked = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];\n \n+ trace_ot_uart_irqs(s->ot_id, s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE],\n+ state_masked);\n+\n for (int index = 0; index < OT_UART_IRQ_NUM; index++) {\n bool level = (state_masked & (1U << index)) != 0;\n qemu_set_irq(s->irqs[index], level);\n@@ -402,6 +407,10 @@ static uint64_t ot_uart_get_baud(OtUARTState *s)\n baud *= clock_get_hz(s->f_clk);\n baud >>= 20;\n \n+ if (baud) {\n+ trace_ot_uart_check_baudrate(s->ot_id, baud);\n+ }\n+\n return baud;\n }\n \n@@ -503,6 +512,10 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n return 0;\n }\n \n+ uint32_t pc = current_cpu->cc->get_pc(current_cpu);\n+ trace_ot_uart_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg),\n+ retvalue, pc);\n+\n return retvalue;\n }\n \n@@ -514,6 +527,9 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n \n hwaddr reg = R32_OFF(addr);\n \n+ uint32_t pc = current_cpu->cc->get_pc(current_cpu);\n+ trace_ot_uart_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), value, pc);\n+\n switch (reg) {\n case R_INTR_STATE:\n /* Write 1 clear */\n@@ -665,6 +681,7 @@ static const VMStateDescription vmstate_ot_uart = {\n };\n \n static const Property ot_uart_properties[] = {\n+ DEFINE_PROP_STRING(\"ot-id\", OtUARTState, ot_id),\n DEFINE_PROP_CHR(\"chardev\", OtUARTState, chr),\n DEFINE_PROP_BOOL(\"oversample-break\", OtUARTState, oversample_break, false),\n DEFINE_PROP_BOOL(\"toggle-break\", OtUARTState, toggle_break, false),\n@@ -716,6 +733,8 @@ static void ot_uart_realize(DeviceState *dev, Error **errp)\n {\n OtUARTState *s = OT_UART(dev);\n \n+ g_assert(s->ot_id);\n+\n s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,\n fifo_trigger_update, s);\n \ndiff --git a/hw/char/trace-events b/hw/char/trace-events\nindex a3fcc77287..17cc9ad2d5 100644\n--- a/hw/char/trace-events\n+++ b/hw/char/trace-events\n@@ -141,3 +141,11 @@ stm32f2xx_usart_receive(char *id, uint8_t chr) \" %s receiving '%c'\"\n # riscv_htif.c\n htif_uart_write_to_host(uint8_t device, uint8_t cmd, uint64_t payload) \"device: %u cmd: %02u payload: %016\" PRIx64\n htif_uart_unknown_device_command(uint8_t device, uint8_t cmd, uint64_t payload) \"device: %u cmd: %02u payload: %016\" PRIx64\n+\n+# ot_uart.c\n+ot_uart_check_baudrate(const char *id, unsigned baud) \"%s: %u bps\"\n+ot_uart_connect_input_clock(const char *id, const char * srcname) \"%s: %s\"\n+ot_uart_debug(const char *id, const char *msg) \"%s: %s\"\n+ot_uart_io_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) \"%s: addr=0x%02x (%s), val=0x%x, pc=0x%x\"\n+ot_uart_io_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) \"%s: addr=0x%02x (%s), val=0x%x, pc=0x%x\"\n+ot_uart_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) \"%s: act:0x%08x msk:0x%08x eff:0x%08x\"\ndiff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c\nindex 97c33d1b53..163d3ac3d3 100644\n--- a/hw/riscv/opentitan.c\n+++ b/hw/riscv/opentitan.c\n@@ -133,6 +133,7 @@ static void lowrisc_ibex_soc_init(Object *obj)\n object_initialize_child(obj, \"plic\", &s->plic, TYPE_SIFIVE_PLIC);\n \n object_initialize_child(obj, \"uart\", &s->uart, TYPE_OT_UART);\n+ object_property_set_str(OBJECT(&s->uart), \"ot-id\", \"uart0\", &error_fatal);\n \n object_initialize_child(obj, \"timer\", &s->timer, TYPE_IBEX_TIMER);\n \ndiff --git a/include/hw/char/ot_uart.h b/include/hw/char/ot_uart.h\nindex 4dc51142f7..2f538e1f6f 100644\n--- a/include/hw/char/ot_uart.h\n+++ b/include/hw/char/ot_uart.h\n@@ -54,6 +54,7 @@ struct OtUARTState {\n bool in_break;\n guint watch_tag;\n \n+ char *ot_id;\n Clock *f_clk;\n \n CharFrontend chr;\n","prefixes":["qemu","v3","09/10"]}