{"id":2223159,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223159/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414155433.483186-10-magnuskulke@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260414155433.483186-10-magnuskulke@linux.microsoft.com>","date":"2026-04-14T15:54:33","name":"[v4,9/9] accel/mshv: disable la57 (5lvl paging)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4885d6d46cf48e424197283954247066d20a9a1e","submitter":{"id":90753,"url":"http://patchwork.ozlabs.org/api/1.1/people/90753/?format=json","name":"Magnus Kulke","email":"magnuskulke@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414155433.483186-10-magnuskulke@linux.microsoft.com/mbox/","series":[{"id":499862,"url":"http://patchwork.ozlabs.org/api/1.1/series/499862/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499862","date":"2026-04-14T15:54:24","name":"Support QEMU cpu models in MSHV accelerator","version":4,"mbox":"http://patchwork.ozlabs.org/series/499862/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223159/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223159/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=nVrCtt4G;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fw84b3mXtz1xtJ\n\tfor ; Wed, 15 Apr 2026 01:55:27 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCg6S-0004nd-Bc; Tue, 14 Apr 2026 11:55:04 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCg6Q-0004nK-Sj\n for qemu-devel@nongnu.org; Tue, 14 Apr 2026 11:55:02 -0400","from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from ) id 1wCg6P-0000HS-8g\n for qemu-devel@nongnu.org; Tue, 14 Apr 2026 11:55:02 -0400","from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.32])\n by linux.microsoft.com (Postfix) with ESMTPSA id 8EE1A20B6F0C;\n Tue, 14 Apr 2026 08:54:58 -0700 (PDT)"],"DKIM-Filter":"OpenDKIM Filter v2.11.0 linux.microsoft.com 8EE1A20B6F0C","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776182100;\n bh=yLPJ4ygZQdPPX5OysbTckl5wWGac8xYnII72KN8oEdQ=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=nVrCtt4GIZoqSx6HfEi6btwY4NFTeeeYA588VRpwCz/18fmSq50mRgOR8strBNM17\n cMxSTrxofHoN3kq7LQmz+JzB4j5xigV5/6DOARMxHJ8K/XEIfrWPHxsXVd43I/FFN1\n sAk8AslsXdtAtmHGo9CnNkb0q+DIa7DJVKutkbi8=","From":"Magnus Kulke ","To":"qemu-devel@nongnu.org","Cc":"Wei Liu , Wei Liu ,\n Magnus Kulke ,\n Magnus Kulke , Zhao Liu ,\n Paolo Bonzini ","Subject":"[PATCH v4 9/9] accel/mshv: disable la57 (5lvl paging)","Date":"Tue, 14 Apr 2026 17:54:33 +0200","Message-Id":"<20260414155433.483186-10-magnuskulke@linux.microsoft.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260414155433.483186-1-magnuskulke@linux.microsoft.com>","References":"<20260414155433.483186-1-magnuskulke@linux.microsoft.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This change disable la57 paging on the mshv hypervisor on both the\nmshv processor feature bitmap and mask the cpuid feature leaf to the\nguest.\n\nSince the removal of hypervisor-assisted gva=>gpa translation in\n1c85a4a3d7 we have seen MMIO errors in guests on la57-enabled hw. We\nwill have to investigate and test this further.\n\nSigned-off-by: Magnus Kulke \nReviewed-by: Anirudh Rayabharam (Microsoft) \n---\n accel/mshv/mshv-all.c | 7 +++++++\n include/system/mshv_int.h | 2 ++\n target/i386/mshv/mshv-cpu.c | 12 ++++++++++++\n 3 files changed, 21 insertions(+)","diff":"diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c\nindex c50641f174..a557623531 100644\n--- a/accel/mshv/mshv-all.c\n+++ b/accel/mshv/mshv-all.c\n@@ -142,6 +142,8 @@ static int create_partition(int mshv_fd, int *vm_fd)\n int ret;\n uint64_t pt_flags, host_proc_features;\n union hv_partition_processor_xsave_features disabled_xsave_features;\n+ union hv_partition_processor_features disabled_partition_features = {0};\n+\n struct mshv_create_partition_v2 args = {0};\n \n QEMU_BUILD_BUG_ON(MSHV_NUM_CPU_FEATURES_BANKS != 2);\n@@ -177,6 +179,11 @@ static int create_partition(int mshv_fd, int *vm_fd)\n }\n args.pt_cpu_fbanks[1] = ~host_proc_features;\n \n+ /* arch-specific features we disable regardless of host support */\n+ mshv_arch_disable_partition_proc_features(&disabled_partition_features);\n+ args.pt_cpu_fbanks[0] |= disabled_partition_features.as_uint64[0];\n+ args.pt_cpu_fbanks[1] |= disabled_partition_features.as_uint64[1];\n+\n /* populate args structure */\n args.pt_flags = pt_flags;\n args.pt_isolation = MSHV_PT_ISOLATION_NONE;\ndiff --git a/include/system/mshv_int.h b/include/system/mshv_int.h\nindex 35386c422f..ca156cdf4b 100644\n--- a/include/system/mshv_int.h\n+++ b/include/system/mshv_int.h\n@@ -94,6 +94,8 @@ void mshv_arch_init_vcpu(CPUState *cpu);\n void mshv_arch_destroy_vcpu(CPUState *cpu);\n void mshv_arch_amend_proc_features(\n union hv_partition_synthetic_processor_features *features);\n+void mshv_arch_disable_partition_proc_features(\n+ union hv_partition_processor_features *disabled_features);\n int mshv_arch_post_init_vm(int vm_fd);\n \n typedef struct mshv_root_hvcall mshv_root_hvcall;\ndiff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\nindex 2c66a52709..433f7a4069 100644\n--- a/target/i386/mshv/mshv-cpu.c\n+++ b/target/i386/mshv/mshv-cpu.c\n@@ -1111,6 +1111,12 @@ void mshv_arch_amend_proc_features(\n features->access_guest_idle_reg = 1;\n }\n \n+void mshv_arch_disable_partition_proc_features(\n+ union hv_partition_processor_features *disabled_features)\n+{\n+ disabled_features->la57_support = 1;\n+}\n+\n static int set_memory_info(const struct hyperv_message *msg,\n struct hv_x64_memory_intercept_message *info)\n {\n@@ -1677,6 +1683,12 @@ uint32_t mshv_get_supported_cpuid(uint32_t func, uint32_t idx, int reg)\n */\n if (func == 0x07 && idx == 0 && reg == R_ECX) {\n ret &= ~CPUID_7_0_ECX_CET_SHSTK;\n+ /*\n+ * LA57 (5-level paging) causes incorrect GVA=>GPA translations\n+ * in the instruction decoder/emulator. Disable until page table\n+ * walk in x86_mmu.c works w/ 5-level paging.\n+ */\n+ ret &= ~CPUID_7_0_ECX_LA57;\n }\n if (func == 0x07 && idx == 0 && reg == R_EDX) {\n ret &= ~CPUID_7_0_EDX_CET_IBT;\n","prefixes":["v4","9/9"]}