{"id":2222929,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222929/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260414024544.2975605-2-duziming2@huawei.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260414024544.2975605-2-duziming2@huawei.com>","date":"2026-04-14T02:45:41","name":"[1/4] PCI: Align proc_bus_pci_write() with pci_write_config()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"922ac5509975dca2abb48b3a927d569c30feebf5","submitter":{"id":92271,"url":"http://patchwork.ozlabs.org/api/1.1/people/92271/?format=json","name":"Ziming Du","email":"duziming2@huawei.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260414024544.2975605-2-duziming2@huawei.com/mbox/","series":[{"id":499767,"url":"http://patchwork.ozlabs.org/api/1.1/series/499767/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499767","date":"2026-04-14T02:45:42","name":"PCI: Fix procfs PCI config access issues","version":1,"mbox":"http://patchwork.ozlabs.org/series/499767/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222929/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222929/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=g7CCuyJR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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Tue, 14 Apr 2026 10:22:25 +0800"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776133352; cv=none;\n b=dnWyOfK9RupoznC9XgWbVv2CM+ntkAxqW2066ujxJI+We+jNb/eZKzxTpYL5spl5jcjB9+O7FndlYw5zTor9B2jYz9msPsBBEFUHBkA9PNH/DKHXVO8UB+mG29X4Wq9L53wAVpjhvbNS8qGY7SjkC5zGt9qQhXibzOhOXvwhdLA=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776133352; c=relaxed/simple;\n\tbh=gLbu8vV6zSfCb2K3PXxLXG24R45tEvAkDPA1Z9QOjU4=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=TQIPQji23CzHabkYvVlcUFPoz1tTCZs2AKUsrKdD6Ahbn/WRVGdTQhra2xpu5neyMxAWzLEPCpQKm6EL3nygp3HH62Ma94lsqYCmYpLSnLEEDORJf5cP2LQ9Z7TGiZCCwKy/LnS1NJqTzB62BnbDPUQWYH+KvdV1NWSs3spodeg=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=g7CCuyJR; arc=none smtp.client-ip=113.46.200.227","dkim-signature":"v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=TcGN3KT4A6NaI0fC1ZrfIs//CROmnI9Y++uz8C6hcO0=;\n\tb=g7CCuyJRfXZEPycaDlHO/eDtVqTu6bJ7MdFAUwDzIlVDFyAsWMYCZ0f07yr+ZXXcGW1BVSWxs\n\tMuLpUT1Wp9K8goDnUy/4k0lh3kHnOARQENoMNTr4CLykLRcZep5VRpEPPIBv4jZcmDhi6NFOCeS\n\t562i9/cH8ayip95FFyHzwiM=","From":"Ziming Du ","To":"","CC":", ,\n\t, ","Subject":"[PATCH 1/4] PCI: Align proc_bus_pci_write() with pci_write_config()","Date":"Tue, 14 Apr 2026 10:45:41 +0800","Message-ID":"<20260414024544.2975605-2-duziming2@huawei.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260414024544.2975605-1-duziming2@huawei.com>","References":"<20260414024544.2975605-1-duziming2@huawei.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"kwepems500002.china.huawei.com (7.221.188.17) To\n kwepemr500012.china.huawei.com (7.202.195.23)"},"content":"proc_bus_pci_write() and pci_write_config() implement essentially the\nsame functionality. To improve consistency across the PCI subsystem,\nalign the implementation in procfs with the sysfs counterpart.\n\nSpecifically:\n - Use dev->cfg_size directly insted of assigning it to 'size'.\n - Rename the variable 'pos' to 'off' and replace 'cnt' with 'size'.\n - Remove the redundant bounds check `if (nbytes >= size)`.\n\nNo functional change intended.\n\nSuggested-by: Bjorn Helgaas \nSigned-off-by: Ziming Du \n---\n drivers/pci/proc.c | 57 +++++++++++++++++++++++-----------------------\n 1 file changed, 28 insertions(+), 29 deletions(-)","diff":"diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c\nindex ce36e35681e8..ff5e4980c99c 100644\n--- a/drivers/pci/proc.c\n+++ b/drivers/pci/proc.c\n@@ -113,73 +113,72 @@ static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,\n {\n \tstruct inode *ino = file_inode(file);\n \tstruct pci_dev *dev = pde_data(ino);\n-\tint pos = *ppos;\n-\tint size = dev->cfg_size;\n-\tint cnt, ret;\n+\tint off = *ppos;\n+\tunsigned int size = nbytes;\n+\tint ret;\n \n \tret = security_locked_down(LOCKDOWN_PCI_ACCESS);\n \tif (ret)\n \t\treturn ret;\n \n-\tif (pos >= size)\n+\tif (off >= dev->cfg_size)\n \t\treturn 0;\n-\tif (nbytes >= size)\n+\tif (off + size > dev->cfg_size) {\n+\t\tsize = dev->cfg_size - off;\n \t\tnbytes = size;\n-\tif (pos + nbytes > size)\n-\t\tnbytes = size - pos;\n-\tcnt = nbytes;\n+\t}\n \n-\tif (!access_ok(buf, cnt))\n+\tif (!access_ok(buf, size))\n \t\treturn -EINVAL;\n \n \tpci_config_pm_runtime_get(dev);\n \n-\tif ((pos & 1) && cnt) {\n+\tif ((off & 1) && size) {\n \t\tunsigned char val;\n \t\t__get_user(val, buf);\n-\t\tpci_user_write_config_byte(dev, pos, val);\n+\t\tpci_user_write_config_byte(dev, off, val);\n \t\tbuf++;\n-\t\tpos++;\n-\t\tcnt--;\n+\t\toff++;\n+\t\tsize--;\n \t}\n \n-\tif ((pos & 3) && cnt > 2) {\n+\tif ((off & 3) && size > 2) {\n \t\t__le16 val;\n \t\t__get_user(val, (__le16 __user *) buf);\n-\t\tpci_user_write_config_word(dev, pos, le16_to_cpu(val));\n+\t\tpci_user_write_config_word(dev, off, le16_to_cpu(val));\n \t\tbuf += 2;\n-\t\tpos += 2;\n-\t\tcnt -= 2;\n+\t\toff += 2;\n+\t\tsize -= 2;\n \t}\n \n-\twhile (cnt >= 4) {\n+\twhile (size >= 4) {\n \t\t__le32 val;\n \t\t__get_user(val, (__le32 __user *) buf);\n-\t\tpci_user_write_config_dword(dev, pos, le32_to_cpu(val));\n+\t\tpci_user_write_config_dword(dev, off, le32_to_cpu(val));\n \t\tbuf += 4;\n-\t\tpos += 4;\n-\t\tcnt -= 4;\n+\t\toff += 4;\n+\t\tsize -= 4;\n \t}\n \n-\tif (cnt >= 2) {\n+\tif (size >= 2) {\n \t\t__le16 val;\n \t\t__get_user(val, (__le16 __user *) buf);\n-\t\tpci_user_write_config_word(dev, pos, le16_to_cpu(val));\n+\t\tpci_user_write_config_word(dev, off, le16_to_cpu(val));\n \t\tbuf += 2;\n-\t\tpos += 2;\n-\t\tcnt -= 2;\n+\t\toff += 2;\n+\t\tsize -= 2;\n \t}\n \n-\tif (cnt) {\n+\tif (size) {\n \t\tunsigned char val;\n \t\t__get_user(val, buf);\n-\t\tpci_user_write_config_byte(dev, pos, val);\n-\t\tpos++;\n+\t\tpci_user_write_config_byte(dev, off, val);\n+\t\toff++;\n \t}\n \n \tpci_config_pm_runtime_put(dev);\n \n-\t*ppos = pos;\n+\t*ppos = off;\n \ti_size_write(ino, dev->cfg_size);\n \treturn nbytes;\n }\n","prefixes":["1/4"]}