{"id":2222925,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222925/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260414024544.2975605-3-duziming2@huawei.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260414024544.2975605-3-duziming2@huawei.com>","date":"2026-04-14T02:45:42","name":"[2/4] PCI: Align proc_bus_pci_read() with pci_read_config()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0de27725f281f2868a0e1d3dc2a3a6456c0f4445","submitter":{"id":92271,"url":"http://patchwork.ozlabs.org/api/1.1/people/92271/?format=json","name":"Ziming Du","email":"duziming2@huawei.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260414024544.2975605-3-duziming2@huawei.com/mbox/","series":[{"id":499767,"url":"http://patchwork.ozlabs.org/api/1.1/series/499767/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499767","date":"2026-04-14T02:45:42","name":"PCI: Fix procfs PCI config access issues","version":1,"mbox":"http://patchwork.ozlabs.org/series/499767/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222925/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222925/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=3oJ7rQSZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-52465-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=\"3oJ7rQSZ\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=113.46.200.224","smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=huawei.com"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvp313kxRz1y2d\n\tfor ; Tue, 14 Apr 2026 12:22:53 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id F27AC3015FD0\n\tfor ; Tue, 14 Apr 2026 02:22:38 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 57E0B311C07;\n\tTue, 14 Apr 2026 02:22:32 +0000 (UTC)","from canpmsgout09.his.huawei.com (canpmsgout09.his.huawei.com\n [113.46.200.224])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F7E730B521;\n\tTue, 14 Apr 2026 02:22:28 +0000 (UTC)","from mail.maildlp.com (unknown [172.19.163.15])\n\tby canpmsgout09.his.huawei.com (SkyGuard) with ESMTPS id 4fvnvF3PZrz1cyPZ;\n\tTue, 14 Apr 2026 10:16:09 +0800 (CST)","from kwepemr500012.china.huawei.com (unknown [7.202.195.23])\n\tby mail.maildlp.com (Postfix) with ESMTPS id 3B8B740539;\n\tTue, 14 Apr 2026 10:22:26 +0800 (CST)","from localhost.localdomain (10.50.85.180) by\n kwepemr500012.china.huawei.com (7.202.195.23) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.11; Tue, 14 Apr 2026 10:22:25 +0800"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776133352; cv=none;\n b=bqXz+8FQ9wM5fpFQmcDp8787L8LLYa0lHe2VgK8nIlC5Xc5OA7MIuyCoDZyi4uYc4PSW5YzWFr4739bb0P9y2EaYqu5V2/6aOU6AihBHemiM434lKObBlp6qy1gU7+FFJtcrGagJk3LorSI3NHyhoBmxKanOMCn4zdoUs+gSMfg=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776133352; c=relaxed/simple;\n\tbh=OYkLhFwawqdifqFscbU3VrkupspsrT9kdrl8ENlfcaA=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=ClifDsAAx3srE01Wr6DBASwg0hAlcEX2iwJ5YjqeU/2nRCnehOgTPQdBwgPSgBHnpVQbjc/wanYdMLF29QKZQDmE+VLPa0uizYx6p5G88GjS0T6xLohzfaAixDhPkRRdiqSmb4EdNgd2RuQT3IcC3GuD/GSUkV10/5Wc6gejX5A=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=3oJ7rQSZ; arc=none smtp.client-ip=113.46.200.224","dkim-signature":"v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=3CqcaT1vZ2gMe5Cbby6fLwgvxf74pWm2QxJf1ILn2LM=;\n\tb=3oJ7rQSZsri+ydi0m7rb2IRDNY3IYhS0SKZGz0K1SsEp4vKU8fQ+H6Umdcme34/L4QeHSOVM7\n\t0t7xwaBkU6jW6sK7bX2LWEqyHsiisuI+jnKwNdKDv/n4l+TuFFHatOWDdDE31/y/oAgy18ex0Vl\n\tQ45+0eHJH1WRTBUlPOoKABc=","From":"Ziming Du ","To":"","CC":", ,\n\t, ","Subject":"[PATCH 2/4] PCI: Align proc_bus_pci_read() with pci_read_config()","Date":"Tue, 14 Apr 2026 10:45:42 +0800","Message-ID":"<20260414024544.2975605-3-duziming2@huawei.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260414024544.2975605-1-duziming2@huawei.com>","References":"<20260414024544.2975605-1-duziming2@huawei.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"kwepems500002.china.huawei.com (7.221.188.17) To\n kwepemr500012.china.huawei.com (7.202.195.23)"},"content":"proc_bus_pci_read() and pci_read_config() implement essentially the\nsame functionality. To improve consistency across the PCI subsystem,\nalign the implementation in procfs with the sysfs counterpart.\n\nSpecifically:\n - Rename the variable 'pos' to 'off' and replace 'cnt' with 'count'.\n - Remove the redundant bounds check `if (nbytes >= size)`.\n\nNo functional change intended.\n\nSuggested-by: Bjorn Helgaas \nSigned-off-by: Ziming Du \n---\n drivers/pci/proc.c | 58 +++++++++++++++++++++++-----------------------\n 1 file changed, 29 insertions(+), 29 deletions(-)","diff":"diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c\nindex ff5e4980c99c..6524280bc903 100644\n--- a/drivers/pci/proc.c\n+++ b/drivers/pci/proc.c\n@@ -29,8 +29,9 @@ static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,\n \t\t\t\t size_t nbytes, loff_t *ppos)\n {\n \tstruct pci_dev *dev = pde_data(file_inode(file));\n-\tunsigned int pos = *ppos;\n-\tunsigned int cnt, size;\n+\tunsigned int off = *ppos;\n+\tunsigned int count = nbytes;\n+\tunsigned int size;\n \n \t/*\n \t * Normal users can read only the standardized portion of the\n@@ -45,66 +46,65 @@ static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,\n \telse\n \t\tsize = 64;\n \n-\tif (pos >= size)\n+\tif (off >= size)\n \t\treturn 0;\n-\tif (nbytes >= size)\n-\t\tnbytes = size;\n-\tif (pos + nbytes > size)\n-\t\tnbytes = size - pos;\n-\tcnt = nbytes;\n+\tif (off + count > size) {\n+\t\tcount = size - off;\n+\t\tnbytes = count;\n+\t}\n \n-\tif (!access_ok(buf, cnt))\n+\tif (!access_ok(buf, count))\n \t\treturn -EINVAL;\n \n \tpci_config_pm_runtime_get(dev);\n \n-\tif ((pos & 1) && cnt) {\n+\tif ((off & 1) && count) {\n \t\tunsigned char val;\n-\t\tpci_user_read_config_byte(dev, pos, &val);\n+\t\tpci_user_read_config_byte(dev, off, &val);\n \t\t__put_user(val, buf);\n \t\tbuf++;\n-\t\tpos++;\n-\t\tcnt--;\n+\t\toff++;\n+\t\tcount--;\n \t}\n \n-\tif ((pos & 3) && cnt > 2) {\n+\tif ((off & 3) && count > 2) {\n \t\tunsigned short val;\n-\t\tpci_user_read_config_word(dev, pos, &val);\n+\t\tpci_user_read_config_word(dev, off, &val);\n \t\t__put_user(cpu_to_le16(val), (__le16 __user *) buf);\n \t\tbuf += 2;\n-\t\tpos += 2;\n-\t\tcnt -= 2;\n+\t\toff += 2;\n+\t\tcount -= 2;\n \t}\n \n-\twhile (cnt >= 4) {\n+\twhile (count >= 4) {\n \t\tunsigned int val;\n-\t\tpci_user_read_config_dword(dev, pos, &val);\n+\t\tpci_user_read_config_dword(dev, off, &val);\n \t\t__put_user(cpu_to_le32(val), (__le32 __user *) buf);\n \t\tbuf += 4;\n-\t\tpos += 4;\n-\t\tcnt -= 4;\n+\t\toff += 4;\n+\t\tcount -= 4;\n \t\tcond_resched();\n \t}\n \n-\tif (cnt >= 2) {\n+\tif (count >= 2) {\n \t\tunsigned short val;\n-\t\tpci_user_read_config_word(dev, pos, &val);\n+\t\tpci_user_read_config_word(dev, off, &val);\n \t\t__put_user(cpu_to_le16(val), (__le16 __user *) buf);\n \t\tbuf += 2;\n-\t\tpos += 2;\n-\t\tcnt -= 2;\n+\t\toff += 2;\n+\t\tcount -= 2;\n \t}\n \n-\tif (cnt) {\n+\tif (count) {\n \t\tunsigned char val;\n-\t\tpci_user_read_config_byte(dev, pos, &val);\n+\t\tpci_user_read_config_byte(dev, off, &val);\n \t\t__put_user(val, buf);\n-\t\tpos++;\n+\t\toff++;\n \t}\n \n \tpci_config_pm_runtime_put(dev);\n \n-\t*ppos = pos;\n+\t*ppos = off;\n \treturn nbytes;\n }\n \n","prefixes":["2/4"]}