{"id":2222897,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222897/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414003001.97571-17-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260414003001.97571-17-philmd@linaro.org>","date":"2026-04-14T00:29:48","name":"[v3,16/27] target/riscv: Register target_get_monitor_def in SysemuCPUOps","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"097b3b1cdf48fe74c08b5ea707ca97de093e7067","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.1/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414003001.97571-17-philmd@linaro.org/mbox/","series":[{"id":499762,"url":"http://patchwork.ozlabs.org/api/1.1/series/499762/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499762","date":"2026-04-14T00:29:32","name":"monitor: Remove need of per-target handlers","version":3,"mbox":"http://patchwork.ozlabs.org/series/499762/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222897/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222897/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=J3rUscBD;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::430;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Rename target_get_monitor_def() as riscv_monitor_get_register_legacy()\nand register it as SysemuCPUOps::monitor_get_register() handler.\nTake care to sign-extend values for 32-bit HARTs.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/riscv/internals.h | 3 +++\n target/riscv/cpu.c | 1 +\n target/riscv/monitor.c | 11 +++++++----\n 3 files changed, 11 insertions(+), 4 deletions(-)","diff":"diff --git a/target/riscv/internals.h b/target/riscv/internals.h\nindex 460346dd6de..28b61d25888 100644\n--- a/target/riscv/internals.h\n+++ b/target/riscv/internals.h\n@@ -245,4 +245,7 @@ static inline int insn_len(uint16_t first_word)\n return (first_word & 3) == 3 ? 4 : 2;\n }\n \n+int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,\n+ int64_t *pval);\n+\n #endif\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 8ac935ac06e..dbd88fa6655 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -2720,6 +2720,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {\n .get_phys_page_debug = riscv_cpu_get_phys_page_debug,\n .write_elf64_note = riscv_cpu_write_elf64_note,\n .write_elf32_note = riscv_cpu_write_elf32_note,\n+ .monitor_get_register = riscv_monitor_get_register_legacy,\n .legacy_vmsd = &vmstate_riscv_cpu,\n };\n #endif\ndiff --git a/target/riscv/monitor.c b/target/riscv/monitor.c\nindex a9d31114442..00a68c26abc 100644\n--- a/target/riscv/monitor.c\n+++ b/target/riscv/monitor.c\n@@ -27,6 +27,7 @@\n #include \"monitor/hmp.h\"\n #include \"monitor/hmp-target.h\"\n #include \"system/memory.h\"\n+#include \"internals.h\"\n \n #ifdef TARGET_RISCV64\n #define PTE_HEADER_FIELDS \"vaddr paddr \"\\\n@@ -311,16 +312,18 @@ static bool reg_is_vreg(const char *name)\n return false;\n }\n \n-int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)\n+int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,\n+ int64_t *pval)\n {\n- CPURISCVState *env = &RISCV_CPU(cs)->env;\n+ RISCVCPU *hart = RISCV_CPU(cs);\n+ CPURISCVState *env = cpu_env(cs);\n target_ulong val = 0;\n uint64_t val64 = 0;\n int i;\n \n if (reg_is_ulong_integer(env, name, &val, false) ||\n reg_is_ulong_integer(env, name, &val, true)) {\n- *pval = val;\n+ *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;\n return 0;\n }\n \n@@ -369,7 +372,7 @@ int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)\n * to do the filtering of the registers that are present.\n */\n if (res == RISCV_EXCP_NONE) {\n- *pval = val;\n+ *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;\n return 0;\n }\n }\n","prefixes":["v3","16/27"]}