{"id":2222847,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413205208.50643-14-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413205208.50643-14-mohamed@unpredictable.fr>","date":"2026-04-13T20:52:05","name":"[v12,13/15] whpx: i386: interrupt priority support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a8928d6db7320caa8f26526718c6a0a6a64b31e1","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/1.1/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413205208.50643-14-mohamed@unpredictable.fr/mbox/","series":[{"id":499753,"url":"http://patchwork.ozlabs.org/api/1.1/series/499753/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499753","date":"2026-04-13T20:51:52","name":"whpx: i386: bug fixes, feature probing and CPUID","version":12,"mbox":"http://patchwork.ozlabs.org/series/499753/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222847/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222847/checks/","tags":{},"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=gxoZouze;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvflH20RTz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 14 Apr 2026 06:53:47 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wCOGt-0007Uh-7m; Mon, 13 Apr 2026 16:52:39 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wCOGr-0007UB-Lx\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 16:52:37 -0400","from ci-2007j-snip4-4.eps.apple.com ([57.103.88.97]\n helo=outbound.ci.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wCOGp-0007xH-8k\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 16:52:37 -0400","from outbound.ci.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-central-1k-10-percent-2 (Postfix) with ESMTPS id\n ABBF81800144; Mon, 13 Apr 2026 20:52:32 +0000 (UTC)","from localhost.localdomain (unknown [17.57.156.36])\n by p00-icloudmta-asmtp-us-central-1k-10-percent-2 (Postfix) with ESMTPSA id\n C88421800169; Mon, 13 Apr 2026 20:52:30 +0000 (UTC)"],"Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776113554; x=1778705554;\n bh=zvIfYiWHwTxnV4KpRpM414Hk+noi+RK5kzhb+FHpHGM=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=gxoZouze6/JuXv73tdpaCz1QJk+CcSmOuWTuuINZ08WSv9rY/d3V29A8GWSHNvH4z9cp+J0DEwiFMGsr6E7OGG8rLOqF/+paAQCLkZkxx85Y+hV8aMIQfDBSnQmRCnPAT5ANvDAJ9u6kn+zxNTN5Gjm2kF6Zpo/wqCSHsKe293wiEM5goH9HgvFgkYnqe7LIXjsZ9K78kCEwAXfOcH7U4UwsoOdYoRyHIKPzQedYlRY8ctDQwDUF65FcjblUj1aYXtMHA06WJ4OfWkwkegL0ssn+YFreGAG3vROY24bt+vrI045NmIkEeu8+WysIhfMKbgypTfcF461zurY+Pd5WKQ==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni <mohamed@unpredictable.fr>","To":"qemu-devel@nongnu.org","Cc":"Phil Dennis-Jordan <phil@philjordan.eu>,\n Pedro Barbuda <pbarbuda@microsoft.com>,\n \"Michael S. Tsirkin\" <mst@redhat.com>, Wei Liu <wei.liu@kernel.org>,\n Paolo Bonzini <pbonzini@redhat.com>, Roman Bolshakov <rbolshakov@ddn.com>,\n Mohamed Mediouni <mohamed@unpredictable.fr>, Zhao Liu <zhao1.liu@intel.com>","Subject":"[PATCH v12 13/15] whpx: i386: interrupt priority support","Date":"Mon, 13 Apr 2026 22:52:05 +0200","Message-ID":"<20260413205208.50643-14-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260413205208.50643-1-mohamed@unpredictable.fr>","References":"<20260413205208.50643-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"cSCQRa8c86lX2ENfa65_AeIdoota3O6t","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDEzMDIwNSBTYWx0ZWRfX08vP5GdyYELX\n tEuCZXsMF5tIph3b4TAjKkK+caPfdlDPQQ3Fc0YlIyV7c6zLIDxtZ4+a+AesLNqHxygOAnwLeJ4\n KuuEQRLbCXfTZoVLAnzNDaMwhdA87chGW3C3llttnQHs4X3iyW1FYVFBo/dI0NkvNJlnz32h9mr\n 9RRzzlV8MZOwJIcHlXpnNr3B8HuOCrs3hKxwCbOEIkfwY2TJAZ4T3a4cdE4xcYySiQYY1GJa4vE\n vhjuGjUhkW36ZOkP/l7/8Cl7ROnyPM97qFo3ymohf1VJ1KHnYIr/3lqYXnsvD6sNEd97Yl3MVW0\n s9R7E5Xt+T2Mp3c9zIH7qyPGsTynl/RAsSmOGC2019JP+YFKaC4Omv2palxzMg=","X-Proofpoint-GUID":"cSCQRa8c86lX2ENfa65_AeIdoota3O6t","X-Authority-Info-Out":"v=2.4 cv=DohbOW/+ c=1 sm=1 tr=0 ts=69dd5791\n cx=c_apl:c_pps:t_out a=2G65uMN5HjSv0sBfM2Yj2w==:117\n a=2G65uMN5HjSv0sBfM2Yj2w==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=NuKELtICf0aykZwt-QIA:9","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-13_03,2026-04-13_04,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=notspam policy=default score=0\n lowpriorityscore=0 clxscore=1030 mlxlogscore=620 adultscore=0 mlxscore=0\n spamscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0\n classifier=spam authscore=0 adjust=0 reason=mlx scancount=1\n engine=8.22.0-2601150000 definitions=main-2604130205","Received-SPF":"pass client-ip=57.103.88.97;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Implement APIC IRR interrupt priorities.\n\nEven with kernel-irqchip=off, Hyper-V is aware of interrupt priorities\nand implements CR8/TPR, with the InterruptPriority field being followed.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n---\n target/i386/whpx/whpx-all.c | 24 ++++++++++++++++++++----\n 1 file changed, 20 insertions(+), 4 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 7a31dc6427..ae15fced0a 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -1588,6 +1588,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n     UINT32 reg_count = 0;\n     WHV_REGISTER_VALUE reg_values[3];\n     WHV_REGISTER_NAME reg_names[3];\n+    int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);\n \n     memset(&new_int, 0, sizeof(new_int));\n     memset(reg_values, 0, sizeof(reg_values));\n@@ -1623,10 +1624,20 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n         }\n     }\n \n+    if (irr == -1) {\n+        if (isa_pic != NULL && pic_get_output(isa_pic)) {\n+            /* In case it's a PIC interrupt */\n+            irr = 0;\n+        } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n+            abort();\n+        }\n+    }\n+\n     /* Get pending hard interruption or replay one that was overwritten */\n     if (!whpx_irqchip_in_kernel()) {\n         if (!vcpu->interruption_pending &&\n-            vcpu->interruptable && (env->eflags & IF_MASK)) {\n+            vcpu->interruptable && (env->eflags & IF_MASK)\n+            && (vcpu->tpr < irr || irr == 0)) {\n             assert(!new_int.InterruptionPending);\n             if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n                 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);\n@@ -1683,13 +1694,17 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n     }\n \n     /* Update the state of the interrupt delivery notification */\n-    if (!vcpu->window_registered &&\n+    if ((!vcpu->window_registered ||\n+        (vcpu->window_priority < irr && vcpu->window_priority != 0) ||\n+        (irr == 0 && vcpu->window_priority != 0)) &&\n         cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n         reg_values[reg_count].DeliverabilityNotifications =\n             (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) {\n-                .InterruptNotification = 1\n+                .InterruptNotification = 1,\n+                .InterruptPriority = irr >> 4\n             };\n         vcpu->window_registered = 1;\n+        vcpu->window_priority = irr;\n         reg_names[reg_count] = WHvX64RegisterDeliverabilityNotifications;\n         reg_count += 1;\n     }\n@@ -1703,7 +1718,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n             reg_names, reg_count, reg_values);\n         if (FAILED(hr)) {\n             error_report(\"WHPX: Failed to set interrupt state registers,\"\n-                         \" hr=%08lx\", hr);\n+                         \" hr=%08lx, InterruptPriority=%i\", hr, irr >> 4);\n         }\n     }\n }\n@@ -1919,6 +1934,7 @@ int whpx_vcpu_run(CPUState *cpu)\n         case WHvRunVpExitReasonX64InterruptWindow:\n             vcpu->ready_for_pic_interrupt = 1;\n             vcpu->window_registered = 0;\n+            vcpu->window_priority = 0;\n             ret = 0;\n             break;\n \n","prefixes":["v12","13/15"]}