{"id":2222810,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222810/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413182456.811543-6-prabhakar.mahadev-lad.rj@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413182456.811543-6-prabhakar.mahadev-lad.rj@bp.renesas.com>","date":"2026-04-13T18:24:55","name":"[v2,5/5] pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in PM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"79537f3c51335697150a3216a8e8c4c875d7b5ef","submitter":{"id":9539,"url":"http://patchwork.ozlabs.org/api/1.1/people/9539/?format=json","name":"Prabhakar","email":"prabhakar.csengg@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413182456.811543-6-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/","series":[{"id":499739,"url":"http://patchwork.ozlabs.org/api/1.1/series/499739/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499739","date":"2026-04-13T18:24:51","name":"pinctrl: renesas: rzg2l: Fix PM register caching","version":2,"mbox":"http://patchwork.ozlabs.org/series/499739/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222810/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222810/checks/","tags":{},"headers":{"Return-Path":"\n <linux-gpio+bounces-35127-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=DWLKszxi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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Add PUPD handling for dedicated pins in the PM\nsave/restore path.\n\nSigned-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>\n---\nv1->v2:\n- New patch\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 19 ++++++++++++++++++-\n 1 file changed, 18 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex be6d229c927b..1aaa78469f52 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -2798,6 +2798,12 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)\n \t\t\t\t\t\t       GFP_KERNEL);\n \t\tif (!dedicated_cache->nod[i])\n \t\t\treturn -ENOMEM;\n+\n+\t\tdedicated_cache->pupd[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,\n+\t\t\t\t\t\t\tsizeof(*dedicated_cache->pupd[i]),\n+\t\t\t\t\t\t\tGFP_KERNEL);\n+\t\tif (!dedicated_cache->pupd[i])\n+\t\t\treturn -ENOMEM;\n \t}\n \n \tpctrl->cache = cache;\n@@ -3136,7 +3142,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t * port offset are close together.\n \t */\n \tfor (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {\n-\t\tbool has_iolh, has_ien, has_sr, has_nod;\n+\t\tbool has_iolh, has_ien, has_sr, has_nod, has_pupd;\n \t\tu32 off, next_off = 0;\n \t\tu64 cfg, next_cfg;\n \t\tu8 pincnt;\n@@ -3160,6 +3166,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t\thas_ien = !!(caps & PIN_CFG_IEN);\n \t\thas_sr = !!(caps & PIN_CFG_SR);\n \t\thas_nod = !!(caps & PIN_CFG_NOD);\n+\t\thas_pupd = !!(caps & PIN_CFG_PUPD);\n \t\tpincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));\n \n \t\tif (has_iolh) {\n@@ -3178,6 +3185,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off),\n \t\t\t\t\t\t cache->nod[0][i]);\n \t\t}\n+\t\tif (has_pupd) {\n+\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),\n+\t\t\t\t\t\t cache->pupd[0][i]);\n+\t\t}\n+\n \t\tif (pincnt >= 4) {\n \t\t\tif (has_iolh) {\n \t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend,\n@@ -3199,6 +3211,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t\t\t\t\t\t\t pctrl->base + NOD(off) + 4,\n \t\t\t\t\t\t\t cache->nod[1][i]);\n \t\t\t}\n+\t\t\tif (has_pupd) {\n+\t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend,\n+\t\t\t\t\t\t\t pctrl->base + PUPD(off) + 4,\n+\t\t\t\t\t\t\t cache->pupd[1][i]);\n+\t\t\t}\n \t\t}\n \t\tcaps = 0;\n \t}\n","prefixes":["v2","5/5"]}