{"id":2222806,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222806/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com>","date":"2026-04-13T18:24:52","name":"[v2,2/5] pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1155a704bd3d275d3bdd878d49c9ae303d247c9e","submitter":{"id":9539,"url":"http://patchwork.ozlabs.org/api/1.1/people/9539/?format=json","name":"Prabhakar","email":"prabhakar.csengg@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/","series":[{"id":499739,"url":"http://patchwork.ozlabs.org/api/1.1/series/499739/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499739","date":"2026-04-13T18:24:51","name":"pinctrl: renesas: rzg2l: Fix PM register caching","version":2,"mbox":"http://patchwork.ozlabs.org/series/499739/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222806/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222806/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=tGjw8SYn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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port < nports; port++) {\n-\t\tbool has_iolh, has_ien, has_pupd, has_smt;\n+\t\tbool has_iolh, has_ien, has_pupd, has_smt, has_sr;\n \t\tu32 off, caps;\n \t\tu8 pincnt;\n \t\tu64 cfg;\n@@ -3024,6 +3037,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \t\thas_ien = !!(caps & PIN_CFG_IEN);\n \t\thas_pupd = !!(caps & PIN_CFG_PUPD);\n \t\thas_smt = !!(caps & PIN_CFG_SMT);\n+\t\thas_sr = !!(caps & PIN_CFG_SR);\n \n \t\tif (suspend)\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);\n@@ -3075,6 +3089,15 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \t\t\t\t\t\t\t cache->smt[1][port]);\n \t\t\t}\n \t\t}\n+\n+\t\tif (has_sr) {\n+\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off),\n+\t\t\t\t\t\t cache->sr[0][port]);\n+\t\t\tif (pincnt >= 4) {\n+\t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off) + 4,\n+\t\t\t\t\t\t\t cache->sr[1][port]);\n+\t\t\t}\n+\t\t}\n \t}\n }\n \n@@ -3089,7 +3112,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t * port offset are close together.\n \t */\n \tfor (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {\n-\t\tbool has_iolh, has_ien;\n+\t\tbool has_iolh, has_ien, has_sr;\n \t\tu32 off, next_off = 0;\n \t\tu64 cfg, next_cfg;\n \t\tu8 pincnt;\n@@ -3110,6 +3133,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t\t/* And apply them in a single shot. */\n \t\thas_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));\n \t\thas_ien = !!(caps & PIN_CFG_IEN);\n+\t\thas_sr = !!(caps & PIN_CFG_SR);\n \t\tpincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));\n \n \t\tif (has_iolh) {\n@@ -3120,7 +3144,10 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),\n \t\t\t\t\t\t cache->ien[0][i]);\n \t\t}\n-\n+\t\tif (has_sr) {\n+\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off),\n+\t\t\t\t\t\t cache->sr[0][i]);\n+\t\t}\n \t\tif (pincnt >= 4) {\n \t\t\tif (has_iolh) {\n \t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend,\n@@ -3132,6 +3159,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t\t\t\t\t\t\t pctrl->base + IEN(off) + 4,\n \t\t\t\t\t\t\t cache->ien[1][i]);\n \t\t\t}\n+\t\t\tif (has_sr) {\n+\t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend,\n+\t\t\t\t\t\t\t pctrl->base + SR(off) + 4,\n+\t\t\t\t\t\t\t cache->sr[1][i]);\n+\t\t\t}\n \t\t}\n \t\tcaps = 0;\n \t}\n","prefixes":["v2","2/5"]}