{"id":2222805,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222805/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413182456.811543-2-prabhakar.mahadev-lad.rj@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413182456.811543-2-prabhakar.mahadev-lad.rj@bp.renesas.com>","date":"2026-04-13T18:24:51","name":"[v2,1/5] pinctrl: renesas: rzg2l: Fix SMT register cache handling","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"934974f520981d69459ade8390dcaa3bf590791f","submitter":{"id":9539,"url":"http://patchwork.ozlabs.org/api/1.1/people/9539/?format=json","name":"Prabhakar","email":"prabhakar.csengg@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413182456.811543-2-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/","series":[{"id":499739,"url":"http://patchwork.ozlabs.org/api/1.1/series/499739/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499739","date":"2026-04-13T18:24:51","name":"pinctrl: renesas: rzg2l: Fix PM register caching","version":2,"mbox":"http://patchwork.ozlabs.org/series/499739/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222805/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222805/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=oFEuZ2oN;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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The previous implementation\ncached only a single SMT register, leading to incomplete save/restore of\nSMT state.\n\nConvert cache->smt to a per-bank array and allocate storage for both\nhalves. Update suspend/resume handling to save and restore both SMT\nregisters when present.\n\nFixes: 837afa592c623 (\"pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control registers\")\nSigned-off-by: Lad Prabhakar \n---\nv1->v2:\n- New patch\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 21 ++++++++++++++-------\n 1 file changed, 14 insertions(+), 7 deletions(-)","diff":"diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex 561e6018fd89..5722cd4c581d 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -335,7 +335,7 @@ struct rzg2l_pinctrl_reg_cache {\n \tu32\t*iolh[2];\n \tu32\t*ien[2];\n \tu32\t*pupd[2];\n-\tu32\t*smt;\n+\tu32\t*smt[2];\n \tu8\tsd_ch[2];\n \tu8\teth_poc[2];\n \tu8\toen;\n@@ -2737,10 +2737,6 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)\n \tif (!cache->pfc)\n \t\treturn -ENOMEM;\n \n-\tcache->smt = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_KERNEL);\n-\tif (!cache->smt)\n-\t\treturn -ENOMEM;\n-\n \tfor (u8 i = 0; i < 2; i++) {\n \t\tu32 n_dedicated_pins = pctrl->data->n_dedicated_pins;\n \n@@ -2759,6 +2755,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)\n \t\tif (!cache->pupd[i])\n \t\t\treturn -ENOMEM;\n \n+\t\tcache->smt[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt[i]),\n+\t\t\t\t\t GFP_KERNEL);\n+\t\tif (!cache->smt[i])\n+\t\t\treturn -ENOMEM;\n+\n \t\t/* Allocate dedicated cache. */\n \t\tdedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,\n \t\t\t\t\t\t\tsizeof(*dedicated_cache->iolh[i]),\n@@ -3066,8 +3067,14 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \t\t\t}\n \t\t}\n \n-\t\tif (has_smt)\n-\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]);\n+\t\tif (has_smt) {\n+\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off),\n+\t\t\t\t\t\t cache->smt[0][port]);\n+\t\t\tif (pincnt >= 4) {\n+\t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off) + 4,\n+\t\t\t\t\t\t\t cache->smt[1][port]);\n+\t\t\t}\n+\t\t}\n \t}\n }\n \n","prefixes":["v2","1/5"]}