{"id":2222764,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222764/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413152326.63738-15-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413152326.63738-15-mohamed@unpredictable.fr>","date":"2026-04-13T15:23:26","name":"[v10,14/14] whpx: i386: fix CPUID[1:EDX].APIC reporting","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"991d5aad6fd1d3e9e414919d65147867a02d25e1","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/1.1/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413152326.63738-15-mohamed@unpredictable.fr/mbox/","series":[{"id":499721,"url":"http://patchwork.ozlabs.org/api/1.1/series/499721/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499721","date":"2026-04-13T15:23:12","name":"whpx: i386: bug fixes, feature probing and CPUID","version":10,"mbox":"http://patchwork.ozlabs.org/series/499721/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222764/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222764/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=g75zPbFX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvWT42lmpz1xtJ\n\tfor ; Tue, 14 Apr 2026 01:26:00 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCJ8u-0005jU-Or; Mon, 13 Apr 2026 11:24:04 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCJ8r-0005cs-4C\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 11:24:01 -0400","from qs-2005i-snip4-4.eps.apple.com ([57.103.86.215]\n helo=outbound.qs.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCJ8n-0000XI-33\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 11:24:00 -0400","from outbound.qs.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-2d-100-percent-10 (Postfix) with ESMTPS id\n A43AF18000A4; Mon, 13 Apr 2026 15:23:51 +0000 (UTC)","from localhost.localdomain (unknown [17.57.155.37])\n by p00-icloudmta-asmtp-us-east-2d-100-percent-10 (Postfix) with ESMTPSA id\n 61BB618001CB; Mon, 13 Apr 2026 15:23:49 +0000 (UTC)"],"Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776093835; x=1778685835;\n bh=M6AkUUrPcxLOfhXzaNmZevrpR2eORr3l/18/Pdjn4vI=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=g75zPbFX9Uvgk1RCyqoRQGzzd7WpkrEsb6FBVcpcD2lM3E8MjLQs1ba5EngMQC50k+j4rL+hRsOUyHZcrQckuGtCIrG6cRwODaBrjyod27Ugi7GlITtDYp/xO6+trRv3KK9JhLNUJ05hhbay4HLjwRQB1u6Gf/DNozBz60FNMx/X27RSrSJAffIxtWUuriNbGS2f+We7NMsjWsBHIuhCzfjMFOK9UzPjtpbMjDmGfu1PegL/us550QsYOmyCjK6LheMB669VkW2nTyJuymXO2ZwHLInBemNMYxR2ZJB2/NAwmyolDiWJpi4B64+TvBXnl6tOmrqPYgMWdpVMzyum4w==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"Zhao Liu , \"Michael S. Tsirkin\" ,\n Paolo Bonzini , Wei Liu ,\n Roman Bolshakov ,\n Pedro Barbuda ,\n Mohamed Mediouni ,\n Phil Dennis-Jordan ","Subject":"[PATCH v10 14/14] whpx: i386: fix CPUID[1:EDX].APIC reporting","Date":"Mon, 13 Apr 2026 17:23:26 +0200","Message-ID":"<20260413152326.63738-15-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260413152326.63738-1-mohamed@unpredictable.fr>","References":"<20260413152326.63738-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"OiZfWjie1kUd0v-0ycLxZjDwKG-_b6iz","X-Proofpoint-GUID":"OiZfWjie1kUd0v-0ycLxZjDwKG-_b6iz","X-Authority-Info-Out":"v=2.4 cv=QKdlhwLL c=1 sm=1 tr=0 ts=69dd0a89\n cx=c_apl:c_pps:t_out a=bsP7O+dXZ5uKcj+dsLqiMw==:117\n a=bsP7O+dXZ5uKcj+dsLqiMw==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=ljJ9V6m273jqBh-Cp98A:9","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDEzMDE1MSBTYWx0ZWRfX91lA5Jj8GUiS\n Lhslujwaa4G3uuzmrF17qtjeT8sVFzEQdo9Hqpgm15W2/oy3vGlUuetkVqT4XGrP/5MME1ydRJ+\n KTjtR4itBHAv6PnPUOez3ELNAB3ixmIailNhJO+2dL2GM7xB0B2A8k+NiIZveI+fAhrIsUHMfT5\n +Dts1DqdyBj9eq7l0n6zFtubJujTnBj8toW+sLWX2QgJFHmO1OuqEPGfrZLIBRipm3GqRsQ4hz5\n kdDOSaNvogNBF0Ld6cedmE2O0nYt/aiAI+/vdCTH0JDqVajhSUPZiw1BgRuMqAMNi/79U4cko+K\n Oq8aFQqHc7F7CVtv9yRr9yj6qn0+3Fq9/Hoxjdoui3kKiT81XZOAxQdzvZ0xVE=","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-13_03,2026-04-13_04,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=notspam policy=default score=0 mlxlogscore=856\n malwarescore=0 adultscore=0 spamscore=0 mlxscore=0\n lowpriorityscore=0\n bulkscore=0 clxscore=1030 phishscore=0 suspectscore=0 classifier=spam\n authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2604130151","Received-SPF":"pass client-ip=57.103.86.215;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Hyper-V always has CPUID[1:EDX].APIC set, even when the APIC isn't enabled yet.\n\nWork around this by also using the APICBASE trap for kernel-irqchip=on.\n\nSigned-off-by: Mohamed Mediouni \n---\n include/system/whpx-common.h | 1 -\n target/i386/whpx/whpx-all.c | 34 ++++++++---------\n target/i386/whpx/whpx-apic.c | 71 ++++++++++++++++++++++++++++++++++--\n 3 files changed, 84 insertions(+), 22 deletions(-)","diff":"diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h\nindex 3406c20fec..79710e2fb3 100644\n--- a/include/system/whpx-common.h\n+++ b/include/system/whpx-common.h\n@@ -8,7 +8,6 @@ struct AccelCPUState {\n bool interruptable;\n bool ready_for_pic_interrupt;\n uint64_t tpr;\n- uint64_t apic_base;\n bool interruption_pending;\n /* Must be the last field as it may have a tail */\n WHV_RUN_VP_EXIT_CONTEXT exit_ctx;\ndiff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 8cd81fffee..9ce73261c2 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -139,7 +139,6 @@ static const WHV_REGISTER_NAME whpx_register_names[] = {\n #ifdef TARGET_X86_64\n WHvX64RegisterKernelGsBase,\n #endif\n- WHvX64RegisterApicBase,\n /* WHvX64RegisterPat, */\n WHvX64RegisterSysenterCs,\n WHvX64RegisterSysenterEip,\n@@ -401,7 +400,6 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n r86 = !(env->cr[0] & CR0_PE_MASK);\n \n vcpu->tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n- vcpu->apic_base = cpu_get_apic_base(x86_cpu->apic_state);\n \n idx = 0;\n \n@@ -519,9 +517,6 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n vcxt.values[idx++].Reg64 = env->kernelgsbase;\n #endif\n \n- assert(whpx_register_names[idx] == WHvX64RegisterApicBase);\n- vcxt.values[idx++].Reg64 = vcpu->apic_base;\n-\n /* WHvX64RegisterPat - Skipped */\n \n assert(whpx_register_names[idx] == WHvX64RegisterSysenterCs);\n@@ -556,6 +551,12 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n error_report(\"WHPX: Failed to set virtual processor context, hr=%08lx\",\n hr);\n }\n+\n+ if (level >= WHPX_LEVEL_FULL_STATE) {\n+ WHV_REGISTER_VALUE apic_base = {};\n+ apic_base.Reg64 = cpu_get_apic_base(X86_CPU(cpu)->apic_state);\n+ whpx_set_reg(cpu, WHvX64RegisterApicBase, apic_base);\n+ }\n }\n \n static int whpx_get_tsc(CPUState *cpu)\n@@ -647,7 +648,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n X86CPU *x86_cpu = X86_CPU(cpu);\n CPUX86State *env = &x86_cpu->env;\n struct whpx_register_set vcxt;\n- uint64_t tpr, apic_base;\n+ uint64_t tpr;\n HRESULT hr;\n int idx;\n int idx_next;\n@@ -779,13 +780,6 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n env->kernelgsbase = vcxt.values[idx++].Reg64;\n #endif\n \n- assert(whpx_register_names[idx] == WHvX64RegisterApicBase);\n- apic_base = vcxt.values[idx++].Reg64;\n- if (apic_base != vcpu->apic_base) {\n- vcpu->apic_base = apic_base;\n- cpu_set_apic_base(x86_cpu->apic_state, vcpu->apic_base);\n- }\n-\n /* WHvX64RegisterPat - Skipped */\n \n assert(whpx_register_names[idx] == WHvX64RegisterSysenterCs);\n@@ -1997,8 +1991,7 @@ int whpx_vcpu_run(CPUState *cpu)\n val = X86_CPU(cpu)->env.apic_bus_freq;\n }\n \n- if (!whpx_irqchip_in_kernel() &&\n- vcpu->exit_ctx.MsrAccess.MsrNumber == MSR_IA32_APICBASE) {\n+ if (vcpu->exit_ctx.MsrAccess.MsrNumber == MSR_IA32_APICBASE) {\n is_known_msr = 1;\n if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) {\n /* Read path unreachable on Hyper-V */\n@@ -2164,6 +2157,13 @@ int whpx_vcpu_run(CPUState *cpu)\n } else {\n reg_values[2].Reg32 &= CPUID_EXT_X2APIC;\n }\n+\n+ /* CPUID[1:EDX].APIC is dynamic */\n+ if (env->features[FEAT_1_EDX] & CPUID_APIC) {\n+ reg_values[3].Reg32 |= CPUID_APIC;\n+ } else {\n+ reg_values[3].Reg32 &= ~CPUID_APIC;\n+ }\n }\n \n /* Dynamic depending on XCR0 and XSS, so query DefaultResult */\n@@ -2725,9 +2725,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n \n memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));\n prop.X64MsrExitBitmap.UnhandledMsrs = 1;\n- if (!whpx_irqchip_in_kernel()) {\n- prop.X64MsrExitBitmap.ApicBaseMsrWrite = 1;\n- }\n+ prop.X64MsrExitBitmap.ApicBaseMsrWrite = 1;\n \n hr = whp_dispatch.WHvSetPartitionProperty(\n whpx->partition,\ndiff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c\nindex f26ecaf6e8..65629ca45f 100644\n--- a/target/i386/whpx/whpx-apic.c\n+++ b/target/i386/whpx/whpx-apic.c\n@@ -90,9 +90,70 @@ static void whpx_get_apic_state(APICCommonState *s,\n apic_next_timer(s, s->initial_count_load_time);\n }\n \n-static int whpx_apic_set_base(APICCommonState *s, uint64_t val)\n+static int apic_set_base_check(APICCommonState *s, uint64_t val)\n {\n- s->apicbase = val;\n+ /* Enable x2apic when x2apic is not supported by CPU */\n+ if (!cpu_has_x2apic_feature(&s->cpu->env) &&\n+ val & MSR_IA32_APICBASE_EXTD) {\n+ return -1;\n+ }\n+\n+ /*\n+ * Transition into invalid state\n+ * (s->apicbase & MSR_IA32_APICBASE_ENABLE == 0) &&\n+ * (s->apicbase & MSR_IA32_APICBASE_EXTD) == 1\n+ */\n+ if (!(val & MSR_IA32_APICBASE_ENABLE) &&\n+ (val & MSR_IA32_APICBASE_EXTD)) {\n+ return -1;\n+ }\n+\n+ /* Invalid transition from disabled mode to x2APIC */\n+ if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) &&\n+ !(s->apicbase & MSR_IA32_APICBASE_EXTD) &&\n+ (val & MSR_IA32_APICBASE_ENABLE) &&\n+ (val & MSR_IA32_APICBASE_EXTD)) {\n+ return -1;\n+ }\n+\n+ /* Invalid transition from x2APIC to xAPIC */\n+ if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) &&\n+ (s->apicbase & MSR_IA32_APICBASE_EXTD) &&\n+ (val & MSR_IA32_APICBASE_ENABLE) &&\n+ !(val & MSR_IA32_APICBASE_EXTD)) {\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n+static int apic_set_base(APICCommonState *s, uint64_t val)\n+{\n+ if (apic_set_base_check(s, val) < 0) {\n+ return -1;\n+ }\n+\n+ s->apicbase = (val & MSR_IA32_APICBASE_BASE) |\n+ (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));\n+ if (!(val & MSR_IA32_APICBASE_ENABLE)) {\n+ s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;\n+ cpu_clear_apic_feature(&s->cpu->env);\n+ }\n+\n+ /* Transition from disabled mode to xAPIC */\n+ if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) &&\n+ (val & MSR_IA32_APICBASE_ENABLE)) {\n+ s->apicbase |= MSR_IA32_APICBASE_ENABLE;\n+ cpu_set_apic_feature(&s->cpu->env);\n+ }\n+\n+ /* Transition from xAPIC to x2APIC */\n+ if (cpu_has_x2apic_feature(&s->cpu->env) &&\n+ !(s->apicbase & MSR_IA32_APICBASE_EXTD) &&\n+ (val & MSR_IA32_APICBASE_EXTD)) {\n+ s->apicbase |= MSR_IA32_APICBASE_EXTD;\n+ }\n+\n return 0;\n }\n \n@@ -235,6 +296,10 @@ static void whpx_apic_mem_write(void *opaque, hwaddr addr,\n static const MemoryRegionOps whpx_apic_io_ops = {\n .read = whpx_apic_mem_read,\n .write = whpx_apic_mem_write,\n+ .impl.min_access_size = 1,\n+ .impl.max_access_size = 4,\n+ .valid.min_access_size = 1,\n+ .valid.max_access_size = 4,\n .endianness = DEVICE_LITTLE_ENDIAN,\n };\n \n@@ -262,7 +327,7 @@ static void whpx_apic_class_init(ObjectClass *klass, const void *data)\n \n k->realize = whpx_apic_realize;\n k->reset = whpx_apic_reset;\n- k->set_base = whpx_apic_set_base;\n+ k->set_base = apic_set_base;\n k->set_tpr = whpx_apic_set_tpr;\n k->get_tpr = whpx_apic_get_tpr;\n k->post_load = whpx_apic_post_load;\n","prefixes":["v10","14/14"]}