{"id":2222762,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222762/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413152326.63738-8-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413152326.63738-8-mohamed@unpredictable.fr>","date":"2026-04-13T15:23:19","name":"[v10,07/14] whpx: i386: kernel-irqchip=off fixes","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"43c129a3bf01c246b07be19f74fa0e2a66f092e5","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/1.1/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413152326.63738-8-mohamed@unpredictable.fr/mbox/","series":[{"id":499721,"url":"http://patchwork.ozlabs.org/api/1.1/series/499721/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499721","date":"2026-04-13T15:23:12","name":"whpx: i386: bug fixes, feature probing and CPUID","version":10,"mbox":"http://patchwork.ozlabs.org/series/499721/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222762/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222762/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=b3oDEX6n;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvWSz6DXJz1xtJ\n\tfor ; Tue, 14 Apr 2026 01:25:55 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCJ8u-0005jg-Rg; Mon, 13 Apr 2026 11:24:04 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCJ8a-0005Wo-5R\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 11:23:45 -0400","from qs-2005l-snip4-11.eps.apple.com ([57.103.86.251]\n helo=outbound.qs.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCJ8X-0000TO-Uc\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 11:23:43 -0400","from outbound.qs.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-2d-100-percent-10 (Postfix) with ESMTPS id\n 71DBF1800114; Mon, 13 Apr 2026 15:23:40 +0000 (UTC)","from localhost.localdomain (unknown [17.57.155.37])\n by p00-icloudmta-asmtp-us-east-2d-100-percent-10 (Postfix) with ESMTPSA id\n EB9C918000A4; Mon, 13 Apr 2026 15:23:38 +0000 (UTC)"],"Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776093821; x=1778685821;\n bh=T/ylQnS/te0fMXN5QyRAvae93avWDOZqU0zT/KgDwLQ=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=b3oDEX6nITMUpVRInSigZuTKl6EaRGe0FCZYfXuh/PuzaGL5pp4SCtO6yYRnOvUUQSfZG/Nv6ADGl8uAhHhqPtzoXN/0OmOSQHJ+n6ouzcDP5tp66CU9TvNfJuMj61nypKGMXFJQHt7R2ToxeujceEyLA0yqHY6D2JryWkjHnmBJaGpmv6sLFdTubn9Toz9sXHhSfALmpQXGpE63yFfmJ5NXibeyBkEKzRC946ZgL/ZqX1kwelY+jgrrnfzr8w7Xg4Wnoidk8sFBZQnOuaECMFRUkW7gBm7NPB3IA4sgtrn4og8rMy+k1qo9mXvecQ1Iicnjup5M3AsHIh1HG/AOUA==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"Zhao Liu , \"Michael S. Tsirkin\" ,\n Paolo Bonzini , Wei Liu ,\n Roman Bolshakov ,\n Pedro Barbuda ,\n Mohamed Mediouni ,\n Phil Dennis-Jordan ","Subject":"[PATCH v10 07/14] whpx: i386: kernel-irqchip=off fixes","Date":"Mon, 13 Apr 2026 17:23:19 +0200","Message-ID":"<20260413152326.63738-8-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260413152326.63738-1-mohamed@unpredictable.fr>","References":"<20260413152326.63738-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-GUID":"TEOdMrv76yBEOJR5aVD2uAiK7Ert-muc","X-Proofpoint-ORIG-GUID":"TEOdMrv76yBEOJR5aVD2uAiK7Ert-muc","X-Authority-Info-Out":"v=2.4 cv=ee0wvrEH c=1 sm=1 tr=0 ts=69dd0a7c\n cx=c_apl:c_pps:t_out a=bsP7O+dXZ5uKcj+dsLqiMw==:117\n a=bsP7O+dXZ5uKcj+dsLqiMw==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=gP1GEkNOX-MqffGxZ4oA:9","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDEzMDE1MSBTYWx0ZWRfXwyfk8bPY4r2E\n a3mtz2kS4sylOx60G+6SgXtLcwKC1hBxaMbeQPqpjswGgxb2L01LCip1HqD6F2YFrHtoWJWbSpN\n W9q4ZCjZboXk7pg+W4u4tZMllTUEkimMpQVwKJp9Zv3/xp+jTVivY6RkN/1qtq6pjZy4OyN2cFX\n fL+bkbkdXRaw8RN8cI9/4Pg2FlgJsJsiXOqcK9DDToxT5X93KTuPkzCdRKc6au5JjsQXmsHdA0Q\n dOYrevdseSvci+UsSz4l6rpBiJJFrYlnRdWiLsrobkISeSUaJ93yYaILgcM7aTVJYJRQTxbiuvD\n inyh7DExInCnLYJfD1pguL8KzzSCW3b1qyR20no1Y9sdtHEmeJlYZp2+MLV7q4=","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-13_03,2026-04-13_04,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=notspam policy=default score=0 bulkscore=0\n spamscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0\n adultscore=0 suspectscore=0 phishscore=0 clxscore=1030 classifier=spam\n authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2604130151","Received-SPF":"pass client-ip=57.103.86.251;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This was really... quite broken. After fixing this,\nWindows boots with kernel-irqchip=off.\n\nSigned-off-by: Mohamed Mediouni \n---\n include/system/whpx-common.h | 1 +\n target/i386/whpx/whpx-all.c | 43 +++++-------------------------------\n 2 files changed, 7 insertions(+), 37 deletions(-)","diff":"diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h\nindex 04289afd97..3406c20fec 100644\n--- a/include/system/whpx-common.h\n+++ b/include/system/whpx-common.h\n@@ -4,6 +4,7 @@\n \n struct AccelCPUState {\n bool window_registered;\n+ int window_priority;\n bool interruptable;\n bool ready_for_pic_interrupt;\n uint64_t tpr;\ndiff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 9827c93df1..62542922a4 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -22,6 +22,8 @@\n #include \"qemu/main-loop.h\"\n #include \"hw/core/boards.h\"\n #include \"hw/intc/ioapic.h\"\n+#include \"hw/intc/i8259.h\"\n+#include \"hw/i386/x86.h\"\n #include \"hw/i386/apic_internal.h\"\n #include \"qemu/error-report.h\"\n #include \"qapi/error.h\"\n@@ -371,28 +373,6 @@ static int whpx_set_tsc(CPUState *cpu)\n return 0;\n }\n \n-/*\n- * The CR8 register in the CPU is mapped to the TPR register of the APIC,\n- * however, they use a slightly different encoding. Specifically:\n- *\n- * APIC.TPR[bits 7:4] = CR8[bits 3:0]\n- *\n- * This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64\n- * and IA-32 Architectures Software Developer's Manual.\n- *\n- * The functions below translate the value of CR8 to TPR and vice versa.\n- */\n-\n-static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr)\n-{\n- return tpr >> 4;\n-}\n-\n-static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8)\n-{\n- return cr8 << 4;\n-}\n-\n void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n {\n struct whpx_state *whpx = &whpx_global;\n@@ -421,7 +401,7 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n v86 = (env->eflags & VM_MASK);\n r86 = !(env->cr[0] & CR0_PE_MASK);\n \n- vcpu->tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+ vcpu->tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n vcpu->apic_base = cpu_get_apic_base(x86_cpu->apic_state);\n \n idx = 0;\n@@ -692,17 +672,6 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n hr);\n }\n \n- if (whpx_irqchip_in_kernel()) {\n- /*\n- * Fetch the TPR value from the emulated APIC. It may get overwritten\n- * below with the value from CR8 returned by\n- * WHvGetVirtualProcessorRegisters().\n- */\n- whpx_apic_get(x86_cpu->apic_state);\n- vcpu->tpr = whpx_apic_tpr_to_cr8(\n- cpu_get_apic_tpr(x86_cpu->apic_state));\n- }\n-\n idx = 0;\n \n /* Indexes for first 16 registers match between HV and QEMU definitions */\n@@ -751,7 +720,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n tpr = vcxt.values[idx++].Reg64;\n if (tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n- cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr));\n+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n }\n \n /* 8 Debug Registers - Skipped */\n@@ -1690,7 +1659,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n \n /* Sync the TPR to the CR8 if was modified during the intercept */\n- tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+ tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n if (tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n reg_values[reg_count].Reg64 = tpr;\n@@ -1737,7 +1706,7 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n if (vcpu->tpr != tpr) {\n vcpu->tpr = tpr;\n bql_lock();\n- cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(vcpu->tpr));\n+ cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n bql_unlock();\n }\n \n","prefixes":["v10","07/14"]}