{"id":2222759,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222759/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413152326.63738-9-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413152326.63738-9-mohamed@unpredictable.fr>","date":"2026-04-13T15:23:20","name":"[v10,08/14] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fdf8a7880917f8e1e26cefbbd6846b1aeb98968d","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/1.1/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413152326.63738-9-mohamed@unpredictable.fr/mbox/","series":[{"id":499721,"url":"http://patchwork.ozlabs.org/api/1.1/series/499721/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499721","date":"2026-04-13T15:23:12","name":"whpx: i386: bug fixes, feature probing and CPUID","version":10,"mbox":"http://patchwork.ozlabs.org/series/499721/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222759/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222759/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=H/EImIWW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvWSd2frVz1xtJ\n\tfor ; Tue, 14 Apr 2026 01:25:37 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCJ90-00062h-83; Mon, 13 Apr 2026 11:24:10 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCJ8d-0005X3-Cv\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 11:23:49 -0400","from qs-2005a-snip4-11.eps.apple.com ([57.103.86.141]\n helo=outbound.qs.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCJ8b-0000U6-6q\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 11:23:46 -0400","from outbound.qs.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-2d-100-percent-10 (Postfix) with ESMTPS id\n 887EE1800190; Mon, 13 Apr 2026 15:23:42 +0000 (UTC)","from localhost.localdomain (unknown [17.57.155.37])\n by p00-icloudmta-asmtp-us-east-2d-100-percent-10 (Postfix) with ESMTPSA id\n 55B831800108; Mon, 13 Apr 2026 15:23:40 +0000 (UTC)"],"Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776093824; x=1778685824;\n bh=9UzhbHGn3KNjJvwbSrpYXcynAdkRNKmx/7n4duVcxcA=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=H/EImIWWofNJ/oQKbexwojsmYODehcKiWx1+D1YO4/da+BGoqMY0AP137XniU3q9kjlcark1tCWc8PSDL/7p5TXi5L6NoRq/HOW6/3eb+CgAsVh/JVyVuOqGoIfqcbXbDvFKnqrkLfG9jN+wr29t+yVLSqNhl5qey8DzXKMj0dY60sQal75VcS8wpwwySDhIYQ8IZGwNREyzivfUpunbF5OwLc0plutHzLO0+fF8cGSrt5T3MN4HI+3UpZ+W2IFLuXAYQrKjqwDS+xup+YY1j+4NgDCikVeFYniepGOsEYJlZjunTdlto4Vn5XkEzg7nvN9Xz46/pFwxrkoqfldUig==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"Zhao Liu , \"Michael S. Tsirkin\" ,\n Paolo Bonzini , Wei Liu ,\n Roman Bolshakov ,\n Pedro Barbuda ,\n Mohamed Mediouni ,\n Phil Dennis-Jordan ","Subject":"[PATCH v10 08/14] whpx: i386: use WHvX64RegisterCr8 only when\n kernel-irqchip=off","Date":"Mon, 13 Apr 2026 17:23:20 +0200","Message-ID":"<20260413152326.63738-9-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260413152326.63738-1-mohamed@unpredictable.fr>","References":"<20260413152326.63738-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-GUID":"QFq6oXE-GucBxWpoaDEOgcIgS6MFCzpb","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDEzMDE1MSBTYWx0ZWRfX2ir0rUN0/guR\n p5lD/3cNAteQRsmvdQ+M2PVJ80laWdmQAJtKNQvQsTvHJeDHpsoiAEAz4oq+/Zj06cwTPoAHBuH\n tkdzdbmqaP5ntWsNTOX3eoGqckLm2ImqB930dgKxQg2aXejKjR+PfS/PE9AnJc3OwR9998WdCua\n VeLyg9ufSHGllfkSZbYt9ReQ+gv8XCRvHfEbAnXvThb/hDArTa8tVlhl0DHWUwUDroMJuBDgl77\n pbWW/V1IhJz/RvEAL77Sxl1P0VQyc/Vqmwcj/gCHEPDWn9d0q/IJdlW4+Y05rA4Lwd7nTd9luYP\n EIIptWsLYnYpAe6VFY5O+Pyi4M9NhXYYmYEgG234ctTnJocQFy4jlDi8nmsy3Q=","X-Authority-Info-Out":"v=2.4 cv=Xqr3+FF9 c=1 sm=1 tr=0 ts=69dd0a7f\n cx=c_apl:c_pps:t_out a=bsP7O+dXZ5uKcj+dsLqiMw==:117\n a=bsP7O+dXZ5uKcj+dsLqiMw==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=4IdwVP5-j8YZXVcKM5MA:9","X-Proofpoint-ORIG-GUID":"QFq6oXE-GucBxWpoaDEOgcIgS6MFCzpb","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-13_03,2026-04-13_04,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=notspam policy=default score=0 suspectscore=0\n spamscore=0 mlxlogscore=867 bulkscore=0\n phishscore=0 mlxscore=0\n malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1030 classifier=spam\n authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2604130151","Received-SPF":"pass client-ip=57.103.86.141;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"When kernel-irqchip=on, manage TPR as part of the APIC state instead entirely.\n\nThis fixes some failure to set state errors.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/whpx/whpx-all.c | 37 ++++++++++++++++++++++---------------\n 1 file changed, 22 insertions(+), 15 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 62542922a4..74b94b799e 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -95,7 +95,6 @@ static const WHV_REGISTER_NAME whpx_register_names[] = {\n WHvX64RegisterCr2,\n WHvX64RegisterCr3,\n WHvX64RegisterCr4,\n- WHvX64RegisterCr8,\n \n /* X64 Debug Registers */\n /*\n@@ -459,8 +458,11 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n vcxt.values[idx++].Reg64 = env->cr[3];\n assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n vcxt.values[idx++].Reg64 = env->cr[4];\n- assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n- vcxt.values[idx++].Reg64 = vcpu->tpr;\n+ /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+ if (!whpx_irqchip_in_kernel()) {\n+ WHV_REGISTER_VALUE cr8 = {.Reg64 = vcpu->tpr};\n+ whpx_set_reg(cpu, WHvX64RegisterCr8, cr8);\n+ }\n \n /* 8 Debug Registers - Skipped */\n \n@@ -716,11 +718,14 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n env->cr[3] = vcxt.values[idx++].Reg64;\n assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n env->cr[4] = vcxt.values[idx++].Reg64;\n- assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n- tpr = vcxt.values[idx++].Reg64;\n- if (tpr != vcpu->tpr) {\n- vcpu->tpr = tpr;\n- cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+\n+ /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+ if (!whpx_irqchip_in_kernel()) {\n+ tpr = vcpu->exit_ctx.VpContext.Cr8;\n+ if (tpr != vcpu->tpr) {\n+ vcpu->tpr = tpr;\n+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+ }\n }\n \n /* 8 Debug Registers - Skipped */\n@@ -1660,7 +1665,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n \n /* Sync the TPR to the CR8 if was modified during the intercept */\n tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n- if (tpr != vcpu->tpr) {\n+ if (!whpx_irqchip_in_kernel() && tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n reg_values[reg_count].Reg64 = tpr;\n qatomic_set(&cpu->exit_request, true);\n@@ -1702,12 +1707,14 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n \n env->eflags = vcpu->exit_ctx.VpContext.Rflags;\n \n- uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n- if (vcpu->tpr != tpr) {\n- vcpu->tpr = tpr;\n- bql_lock();\n- cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n- bql_unlock();\n+ if (!whpx_irqchip_in_kernel()) {\n+ uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n+ if (vcpu->tpr != tpr) {\n+ vcpu->tpr = tpr;\n+ bql_lock();\n+ cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n+ bql_unlock();\n+ }\n }\n \n vcpu->interruption_pending =\n","prefixes":["v10","08/14"]}