{"id":2222733,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222733/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-15-3aeb53022c32@oss.qualcomm.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413-waveshare-dsi-touch-v3-15-3aeb53022c32@oss.qualcomm.com>","date":"2026-04-13T14:05:38","name":"[v3,15/21] drm/panel: jadard-jd9365da-h3: support Waveshare WXGA DSI panels","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"99d2182f1dd1c697ccf1ec1684a7f1b4e6df949d","submitter":{"id":90483,"url":"http://patchwork.ozlabs.org/api/1.1/people/90483/?format=json","name":"Dmitry Baryshkov","email":"dmitry.baryshkov@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-15-3aeb53022c32@oss.qualcomm.com/mbox/","series":[{"id":499710,"url":"http://patchwork.ozlabs.org/api/1.1/series/499710/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499710","date":"2026-04-13T14:05:24","name":"drm/panel: support Waveshare DSI TOUCH kits","version":3,"mbox":"http://patchwork.ozlabs.org/series/499710/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222733/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222733/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com 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Vetter ,\n Maarten Lankhorst ,\n Maxime Ripard ,\n Thomas Zimmermann ,\n Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley ,\n Cong Yang ,\n Ondrej Jirman ,\n Javier Martinez Canillas ,\n Jagan Teki , Liam Girdwood ,\n Mark Brown , Linus Walleij ,\n Bartosz Golaszewski ,\n Jie Gan ","Cc":"dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,\n Riccardo Mereu ","X-Mailer":"b4 0.15.1","X-Developer-Signature":"v=1; a=openpgp-sha256; l=27749;\n i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id;\n bh=JpdFVjFOA408Dyve5igXEKyXmePeVuQuHMaoR/cbAbE=;\n b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBp3PgoKNPynlErXs4q5Z05hQZ+IWKSE9WfoBhNC\n 2RLi1hwqaGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCadz4KAAKCRCLPIo+Aiko\n 1SnAB/9yyEZ45QALzIXQlpL7s5VOSLneUWQ86B+cMqrLq6PvkcWKD2vhzlbADurkRC+J+Uilkq6\n wZLU4U0Hn5VzWd1PDL7C6t5nSEDT/NjfZRVdmjvqDH7VY6gbBPkz/gSMI6rgVOmAMarx+6nhbVq\n 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definitions=main-2604130138"},"content":"Add configuration for several Waveshare 8.0\" and 10.1\" WXGA DSI panels\nusing JD9365 controller\n\nTested-by: Riccardo Mereu \nSigned-off-by: Dmitry Baryshkov \n---\n drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 568 +++++++++++++++++++++++\n 1 file changed, 568 insertions(+)","diff":"diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\nindex 61d67efed379..7744c66514c9 100644\n--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n@@ -2067,6 +2067,566 @@ static const struct jadard_panel_desc waveshare_4_0_inch_c_desc = {\n \t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n };\n \n+static int waveshare_8_0_a_init(struct jadard *jadard)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7e);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x4e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xb7);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xb7);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x70);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x63);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x54);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x23);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xf8);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x7b);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59);\n+\tif (jadard->dsi->lanes != 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);\n+\t}\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(60);\n+\n+\treturn 0;\n+}\n+\n+static const struct drm_display_mode waveshare_8_0_a_mode = {\n+\t.clock\t\t= (800 + 40 + 20 + 20) * (1280 + 30 + 12 + 4) * 60 / 1000,\n+\n+\t.hdisplay\t= 800,\n+\t.hsync_start\t= 800 + 40,\n+\t.hsync_end\t= 800 + 40 + 20,\n+\t.htotal\t\t= 800 + 40 + 20 + 20,\n+\n+\t.vdisplay\t= 1280,\n+\t.vsync_start\t= 1280 + 30,\n+\t.vsync_end\t= 1280 + 30 + 12,\n+\t.vtotal\t\t= 1280 + 30 + 12 + 4,\n+\n+\t.width_mm\t= 107,\n+\t.height_mm\t= 172,\n+\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+};\n+\n+static const struct jadard_panel_desc waveshare_8_0_inch_a_desc = {\n+\t.mode_4ln = &waveshare_8_0_a_mode,\n+\t.mode_2ln = &waveshare_8_0_a_mode,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_8_0_a_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n+static const struct drm_display_mode waveshare_10_1_a_mode = {\n+\t.clock\t\t= (800 + 40 + 20 + 20) * (1280 + 20 + 20 + 4) * 60 / 1000,\n+\n+\t.hdisplay\t= 800,\n+\t.hsync_start\t= 800 + 40,\n+\t.hsync_end\t= 800 + 40 + 20,\n+\t.htotal\t\t= 800 + 40 + 20 + 20,\n+\n+\t.vdisplay\t= 1280,\n+\t.vsync_start\t= 1280 + 20,\n+\t.vsync_end\t= 1280 + 20 + 20,\n+\t.vtotal\t\t= 1280 + 20 + 20 + 4,\n+\n+\t.width_mm\t= 135,\n+\t.height_mm\t= 216,\n+\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+};\n+\n+static int waveshare_10_1_a_init(struct jadard *jadard)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3b);\n+\telse {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x38);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x38);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xaf);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xaf);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0d);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6b);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5c);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5b);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4f);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4d);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2b);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3d);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x41);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2a);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x44);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x5a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x4e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x20);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0f);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x59);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4c);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x48);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x3a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x26);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6b);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5c);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5b);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4f);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4d);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2b);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3d);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x41);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2a);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x63);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x44);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x52);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x5a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x4e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0f);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x59);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4c);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x48);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x3a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x26);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x17);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x37);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x37);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x42);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x42);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x40);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x57);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x57);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x77);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x77);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x17);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x41);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x41);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x40);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x40);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x5e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x57);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x57);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x77);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x77);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x48);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x16);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x34);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1d);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xdd);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3f);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x82);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);\n+\tif (jadard->dsi->lanes != 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);\n+\t}\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x0c);\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(60);\n+\n+\treturn dsi_ctx.accum_err;\n+}\n+\n+static const struct jadard_panel_desc waveshare_10_1_inch_a_desc = {\n+\t.mode_4ln = &waveshare_10_1_a_mode,\n+\t.mode_2ln = &waveshare_10_1_a_mode,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_10_1_a_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\tMIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n static int jadard_dsi_probe(struct mipi_dsi_device *dsi)\n {\n \tstruct device *dev = &dsi->dev;\n@@ -2198,6 +2758,14 @@ static const struct of_device_id jadard_of_match[] = {\n \t\t.compatible = \"waveshare,4.0-dsi-touch-c\",\n \t\t.data = &waveshare_4_0_inch_c_desc\n \t},\n+\t{\n+\t\t.compatible = \"waveshare,8.0-dsi-touch-a\",\n+\t\t.data = &waveshare_8_0_inch_a_desc\n+\t},\n+\t{\n+\t\t.compatible = \"waveshare,10.1-dsi-touch-a\",\n+\t\t.data = &waveshare_10_1_inch_a_desc\n+\t},\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, jadard_of_match);\n","prefixes":["v3","15/21"]}