{"id":2222730,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222730/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-16-3aeb53022c32@oss.qualcomm.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413-waveshare-dsi-touch-v3-16-3aeb53022c32@oss.qualcomm.com>","date":"2026-04-13T14:05:39","name":"[v3,16/21] drm/panel: jadard-jd9365da-h3: support Waveshare 720p DSI panels","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"889d8593f2985e16f4dfb841953cc0c874fdd194","submitter":{"id":90483,"url":"http://patchwork.ozlabs.org/api/1.1/people/90483/?format=json","name":"Dmitry Baryshkov","email":"dmitry.baryshkov@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-16-3aeb53022c32@oss.qualcomm.com/mbox/","series":[{"id":499710,"url":"http://patchwork.ozlabs.org/api/1.1/series/499710/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499710","date":"2026-04-13T14:05:24","name":"drm/panel: support Waveshare DSI TOUCH kits","version":3,"mbox":"http://patchwork.ozlabs.org/series/499710/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222730/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222730/checks/","tags":{},"headers":{"Return-Path":"\n <linux-gpio+bounces-35111-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass 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<neil.armstrong@linaro.org>,\n        Jessica Zhang <jesszhan0024@gmail.com>,\n        David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n        Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,\n        Maxime Ripard <mripard@kernel.org>,\n        Thomas Zimmermann <tzimmermann@suse.de>,\n Rob Herring <robh@kernel.org>,\n        Krzysztof Kozlowski <krzk+dt@kernel.org>,\n        Conor Dooley <conor+dt@kernel.org>,\n        Cong Yang <yangcong5@huaqin.corp-partner.google.com>,\n        Ondrej Jirman <megi@xff.cz>,\n        Javier Martinez Canillas <javierm@redhat.com>,\n        Jagan Teki <jagan@edgeble.ai>, Liam Girdwood <lgirdwood@gmail.com>,\n        Mark Brown <broonie@kernel.org>, Linus Walleij <linusw@kernel.org>,\n        Bartosz Golaszewski <brgl@kernel.org>,\n        Jie Gan <jie.gan@oss.qualcomm.com>","Cc":"dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,\n        linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,\n        Riccardo Mereu <r.mereu@arduino.cc>","X-Mailer":"b4 0.15.1","X-Developer-Signature":"v=1; a=openpgp-sha256; l=15643;\n i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id;\n bh=i/SoNHcSayVBIBioV2QuYYiEm2da1S4Pj0J5C0tmjFM=;\n b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBp3Pgo2lBnKTQi8guyD+eeglC2fjYuNeeZ2GpgB\n f9iUPrSNO6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCadz4KAAKCRCLPIo+Aiko\n 1RfSCACsy9QBg7E9w5/7KiMfyfj4e4mq5epA+CkvHgYhx9Jp6KfkQumujQ2hlXcK5rYjT31CPLZ\n aL23RqEAlVCtwjCrffCLdDSIgt3i7+RxsWMciMyoCstFdtHUKxAc4zZ4jkBoyK2XBbBPHMNSHYf\n 8TNnwy3XnkH1AyKR/rRhIedHq2QXByUXQ6VKBdWp2VfCAKoEnZVI3IhmqdWe3mZJiPQCRa5fbsr\n GTOZCmq7U0S+Npg014/2y+a6Y3Jr4D97j4q7ReYhGs621U9krEM+02XlBA70IP2xnd4oKUs84JN\n 0w+Y4uH4HDECKDQsnw6/k1p4ZgEEX6i4QO4GS3DrNIL/f4ow","X-Developer-Key":"i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp;\n fpr=8F88381DD5C873E4AE487DA5199BF1243632046A","X-Proofpoint-ORIG-GUID":"afNXQDrXMr5vLrS1bEiF-dBc8YeXyawL","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDEzMDEzOCBTYWx0ZWRfXw0Du4xiA60OK\n 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engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-13_03,2026-04-13_03,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 malwarescore=0\n bulkscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604130138"},"content":"Add configuration for Waveshare 9.0\" and 10.1\" 720p DSI panels using\nJD9365 controller.\n\nTested-by: Riccardo Mereu <r.mereu@arduino.cc>\nSigned-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>\n---\n drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 312 +++++++++++++++++++++++\n 1 file changed, 312 insertions(+)","diff":"diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\nindex 7744c66514c9..6fff3299f4ad 100644\n--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n@@ -21,6 +21,8 @@\n #include <linux/of.h>\n #include <linux/regulator/consumer.h>\n \n+#include <video/mipi_display.h>\n+\n struct jadard;\n \n struct jadard_panel_desc {\n@@ -2283,6 +2285,49 @@ static const struct jadard_panel_desc waveshare_8_0_inch_a_desc = {\n \t\t      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n };\n \n+static int waveshare_10_1_b_init(struct jadard *jadard);\n+\n+static const struct jadard_panel_desc waveshare_9_0_inch_b_desc = {\n+\t.mode_4ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 60,\n+\t\t.hsync_end\t= 720 + 60 + 60,\n+\t\t.htotal\t\t= 720 + 60 + 60 + 4,\n+\n+\t\t.vdisplay\t= 1280,\n+\t\t.vsync_start\t= 1280 + 16,\n+\t\t.vsync_end\t= 1280 + 16 + 12,\n+\t\t.vtotal\t\t= 1280 + 16 + 12 + 4,\n+\n+\t\t.width_mm\t= 114,\n+\t\t.height_mm\t= 196,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.mode_2ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 50,\n+\t\t.hsync_end\t= 720 + 50 + 50,\n+\t\t.htotal\t\t= 720 + 50 + 50 + 50,\n+\n+\t\t.vdisplay\t= 1280,\n+\t\t.vsync_start\t= 1280 + 26,\n+\t\t.vsync_end\t= 1280 + 26 + 12,\n+\t\t.vtotal\t\t= 1280 + 26 + 12 + 4,\n+\n+\t\t.width_mm\t= 114,\n+\t\t.height_mm\t= 196,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_10_1_b_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\tMIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n static const struct drm_display_mode waveshare_10_1_a_mode = {\n \t.clock\t\t= (800 + 40 + 20 + 20) * (1280 + 20 + 20 + 4) * 60 / 1000,\n \n@@ -2627,6 +2672,265 @@ static const struct jadard_panel_desc waveshare_10_1_inch_a_desc = {\n \t\tMIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n };\n \n+static int waveshare_10_1_b_init(struct jadard *jadard)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x3f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xbf);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xbf);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x74);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x7e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x24);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x38);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x65);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x52);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x23);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x3f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x34);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x27);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x24);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x65);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x52);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x23);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x3f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x34);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x27);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x24);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x51);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x55);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x51);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x51);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x55);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x11);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x15);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x11);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x11);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x15);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x11);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x66);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x55);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x13);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x66);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xe3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x21);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x66);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1d);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(5);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_TEAR_ON);\n+\n+\treturn 0;\n+}\n+\n+static const struct jadard_panel_desc waveshare_10_1_inch_b_desc = {\n+\t.mode_4ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 60,\n+\t\t.hsync_end\t= 720 + 60 + 60,\n+\t\t.htotal\t\t= 720 + 60 + 60 + 4,\n+\n+\t\t.vdisplay\t= 1280,\n+\t\t.vsync_start\t= 1280 + 16,\n+\t\t.vsync_end\t= 1280 + 16 + 12,\n+\t\t.vtotal\t\t= 1280 + 16 + 12 + 4,\n+\n+\t\t.width_mm\t= 125,\n+\t\t.height_mm\t= 222,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.mode_2ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 50,\n+\t\t.hsync_end\t= 720 + 50 + 50,\n+\t\t.htotal\t\t= 720 + 50 + 50 + 50,\n+\n+\t\t.vdisplay\t= 1280,\n+\t\t.vsync_start\t= 1280 + 26,\n+\t\t.vsync_end\t= 1280 + 26 + 12,\n+\t\t.vtotal\t\t= 1280 + 26 + 12 + 4,\n+\n+\t\t.width_mm\t= 125,\n+\t\t.height_mm\t= 222,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_10_1_b_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\tMIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n static int jadard_dsi_probe(struct mipi_dsi_device *dsi)\n {\n \tstruct device *dev = &dsi->dev;\n@@ -2762,10 +3066,18 @@ static const struct of_device_id jadard_of_match[] = {\n \t\t.compatible = \"waveshare,8.0-dsi-touch-a\",\n \t\t.data = &waveshare_8_0_inch_a_desc\n \t},\n+\t{\n+\t\t.compatible = \"waveshare,9.0-dsi-touch-b\",\n+\t\t.data = &waveshare_9_0_inch_b_desc\n+\t},\n \t{\n \t\t.compatible = \"waveshare,10.1-dsi-touch-a\",\n \t\t.data = &waveshare_10_1_inch_a_desc\n \t},\n+\t{\n+\t\t.compatible = \"waveshare,10.1-dsi-touch-b\",\n+\t\t.data = &waveshare_10_1_inch_b_desc\n+\t},\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, jadard_of_match);\n","prefixes":["v3","16/21"]}