{"id":2222727,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222727/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-14-3aeb53022c32@oss.qualcomm.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413-waveshare-dsi-touch-v3-14-3aeb53022c32@oss.qualcomm.com>","date":"2026-04-13T14:05:37","name":"[v3,14/21] drm/panel: jadard-jd9365da-h3: support Waveshare round DSI panels","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b68d4ff5f0c0eecd0ceb48f1a8aad724d71755d9","submitter":{"id":90483,"url":"http://patchwork.ozlabs.org/api/1.1/people/90483/?format=json","name":"Dmitry Baryshkov","email":"dmitry.baryshkov@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-14-3aeb53022c32@oss.qualcomm.com/mbox/","series":[{"id":499710,"url":"http://patchwork.ozlabs.org/api/1.1/series/499710/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499710","date":"2026-04-13T14:05:24","name":"drm/panel: support Waveshare DSI TOUCH kits","version":3,"mbox":"http://patchwork.ozlabs.org/series/499710/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222727/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222727/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com 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Vetter ,\n Maarten Lankhorst ,\n Maxime Ripard ,\n Thomas Zimmermann ,\n Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley ,\n Cong Yang ,\n Ondrej Jirman ,\n Javier Martinez Canillas ,\n Jagan Teki , Liam Girdwood ,\n Mark Brown , Linus Walleij ,\n Bartosz Golaszewski ,\n Jie Gan ","Cc":"dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,\n Riccardo Mereu ","X-Mailer":"b4 0.15.1","X-Developer-Signature":"v=1; a=openpgp-sha256; l=24423;\n i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id;\n bh=MIfetJdxtR4RP3QkPd0ovBX9kWXJpuY2wobhSOEc4s4=;\n b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBp3PgozqkuupRh1rfb+qM9/pA7DoBMvABs98Jce\n l6sv6N6Sn2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCadz4KAAKCRCLPIo+Aiko\n 1VKAB/0Zg+Xrk9u6YEA2ISE4iS4oDJQMOgz+sCYEpEp0rRE/xx331UwwcyH+UPvkjj/sWFMV1b9\n yS4YgRUbNJOt3xv8T713EBjeQq7K0i2qnKFDwHEj6yEQxE262O3QhFBJz/IQnXKy2qYc/yYLxUD\n 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WB+EFOMHoBMyUBknW5MqP+cQDHBPHfz0ooF2QldWr706OHlBL11cx2xpbjqeDpbPcWrBleCCpm2\n TuJ8Wm44f3jFoRIv/NwBu/FrSwuw2AJnfjH38yp9rllNAG4vhcNAjYEjvAEF1hI94dZ+QQroyw6\n LZOAzstegDIm0O01cKImuQ6IBEBmG5h6aY5izfvA9L1izPU4Nos4FWJ6AU4yHnNXWIc+fbRwHSs\n 2BzYsnUnKRNvHXbG/0BXKpYfPnrGzPLozCEkAqQZec1P5c/TXUyuHuYHCFUQu39SEL6jFWLkBc2\n fjbM1QXaaPZ77VYV5Nw==","X-Proofpoint-GUID":"aDfuXPB7lhLqh567p11Rp8nPri73jpyX","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-13_03,2026-04-13_03,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 phishscore=0\n malwarescore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604130138"},"content":"Add configuration for Waveshare 3.4\" and 4.0\" round DSI panels using\nJD9365 controller.\n\nTested-by: Riccardo Mereu \nSigned-off-by: Dmitry Baryshkov \n---\n drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 476 +++++++++++++++++++++++\n 1 file changed, 476 insertions(+)","diff":"diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\nindex bc079b97cfb3..61d67efed379 100644\n--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n@@ -1599,6 +1599,474 @@ static const struct jadard_panel_desc taiguan_xti05101_01a_desc = {\n \t.enter_sleep_to_reset_down_delay_ms = 100,\n };\n \n+static int waveshare_3_4_c_init(struct jadard *jadard)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xd0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xd0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x64);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0xc7);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x1b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x16);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x2f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x32);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x53);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x4c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x20);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x16);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x2f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x32);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x53);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x4c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x20);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x0f);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x42);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0xa6);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xd9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(5);\n+\tmipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);\n+\n+\treturn dsi_ctx.accum_err;\n+}\n+\n+static const struct jadard_panel_desc waveshare_3_4_inch_c_desc = {\n+\t.mode_2ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (800 + 40 + 20 + 20) * (800 + 24 + 4 + 12) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 800,\n+\t\t.hsync_start\t= 800 + 40,\n+\t\t.hsync_end\t= 800 + 40 + 20,\n+\t\t.htotal\t\t= 800 + 40 + 20 + 20,\n+\n+\t\t.vdisplay\t= 800,\n+\t\t.vsync_start\t= 800 + 24,\n+\t\t.vsync_end\t= 800 + 24 + 4,\n+\t\t.vtotal\t\t= 800 + 24 + 4 + 12,\n+\n+\t\t.width_mm\t= 88,\n+\t\t.height_mm\t= 88,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.lanes = 2,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_3_4_c_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n+static int waveshare_4_0_c_init(struct jadard *jadard)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xd0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xd0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x64);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0xc7);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x1b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x16);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x2f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x32);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x53);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x4c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x20);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x16);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x2f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x32);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x53);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x4c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x20);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x0f);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x42);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0xa6);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xd9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(5);\n+\tmipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);\n+\n+\treturn dsi_ctx.accum_err;\n+}\n+\n+static const struct jadard_panel_desc waveshare_4_0_inch_c_desc = {\n+\t.mode_2ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 40 + 20 + 20) * (720 + 24 + 4 + 12) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 40,\n+\t\t.hsync_end\t= 720 + 40 + 20,\n+\t\t.htotal\t\t= 720 + 40 + 20 + 20,\n+\n+\t\t.vdisplay\t= 720,\n+\t\t.vsync_start\t= 720 + 24,\n+\t\t.vsync_end\t= 720 + 24 + 4,\n+\t\t.vtotal\t\t= 720 + 24 + 4 + 12,\n+\n+\t\t.width_mm\t= 88,\n+\t\t.height_mm\t= 88,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.lanes = 2,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_4_0_c_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n static int jadard_dsi_probe(struct mipi_dsi_device *dsi)\n {\n \tstruct device *dev = &dsi->dev;\n@@ -1722,6 +2190,14 @@ static const struct of_device_id jadard_of_match[] = {\n \t\t.compatible = \"taiguanck,xti05101-01a\",\n \t\t.data = &taiguan_xti05101_01a_desc\n \t},\n+\t{\n+\t\t.compatible = \"waveshare,3.4-dsi-touch-c\",\n+\t\t.data = &waveshare_3_4_inch_c_desc\n+\t},\n+\t{\n+\t\t.compatible = \"waveshare,4.0-dsi-touch-c\",\n+\t\t.data = &waveshare_4_0_inch_c_desc\n+\t},\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, jadard_of_match);\n","prefixes":["v3","14/21"]}