{"id":2222679,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222679/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413122233.375945-3-ajay.nandam@oss.qualcomm.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413122233.375945-3-ajay.nandam@oss.qualcomm.com>","date":"2026-04-13T12:22:32","name":"[v1,2/3] pinctrl: qcom: lpass-lpi: Fix GPIO register access helper return types","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"66728c490f7ef2ecd90e600440228ed7a55c98ee","submitter":{"id":93131,"url":"http://patchwork.ozlabs.org/api/1.1/people/93131/?format=json","name":"Ajay Kumar Nandam","email":"ajay.nandam@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413122233.375945-3-ajay.nandam@oss.qualcomm.com/mbox/","series":[{"id":499692,"url":"http://patchwork.ozlabs.org/api/1.1/series/499692/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499692","date":"2026-04-13T12:22:30","name":"pinctrl: qcom: lpass-lpi: PM clock framework cleanup and fixes","version":1,"mbox":"http://patchwork.ozlabs.org/series/499692/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222679/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222679/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=onLJ9rIS;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=A2eOKyAv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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This mixes data\nreturn with status and is inconsistent with common kernel helper\nconventions.\n\nRework lpi_gpio_read() and lpi_gpio_write() to return an int status and\nuse output parameters to pass register values. Update all callers to\nmatch the new helper interface.\n\nThis change fixes the helper API and resulting call sites without\nintending any functional change in GPIO or pinctrl behavior.\n\nSigned-off-by: Ajay Kumar Nandam \n---\n drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 66 +++++++++++++++++-------\n 1 file changed, 47 insertions(+), 19 deletions(-)","diff":"diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c\nindex 6d50e06ef..d108e7321 100644\n--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c\n+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c\n@@ -39,22 +39,26 @@ struct lpi_pinctrl {\n };\n \n static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,\n-\t\t\t unsigned int addr)\n+\t\t\t unsigned int addr, u32 *val)\n {\n \tu32 pin_offset;\n+\tint ret;\n \n \tif (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)\n \t\tpin_offset = state->data->groups[pin].pin_offset;\n \telse\n \t\tpin_offset = LPI_TLMM_REG_OFFSET * pin;\n \n-\treturn ioread32(state->tlmm_base + pin_offset + addr);\n+\t*val = ioread32(state->tlmm_base + pin_offset + addr);\n+\n+\treturn 0;\n }\n \n static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,\n \t\t\t unsigned int addr, unsigned int val)\n {\n \tu32 pin_offset;\n+\tint ret;\n \n \tif (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)\n \t\tpin_offset = state->data->groups[pin].pin_offset;\n@@ -107,7 +111,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,\n {\n \tstruct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n \tconst struct lpi_pingroup *g = &pctrl->data->groups[group];\n-\tu32 val;\n+\tu32 val, io_val;\n+\tint ret;\n \tint i, pin = g->pin;\n \n \tfor (i = 0; i < g->nfuncs; i++) {\n@@ -119,7 +124,9 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,\n \t\treturn -EINVAL;\n \n \tmutex_lock(&pctrl->lock);\n-\tval = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);\n+\tret = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG, &val);\n+\tif (ret)\n+\t\tgoto out_unlock;\n \n \t/*\n \t * If this is the first time muxing to GPIO and the direction is\n@@ -129,24 +136,28 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,\n \t */\n \tif (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) &&\n \t !test_and_set_bit(group, pctrl->ever_gpio)) {\n-\t\tu32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG);\n+\t\tret = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG, &io_val);\n+\t\tif (ret)\n+\t\t\tgoto out_unlock;\n \n \t\tif (io_val & LPI_GPIO_VALUE_IN_MASK) {\n \t\t\tif (!(io_val & LPI_GPIO_VALUE_OUT_MASK))\n-\t\t\t\tlpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,\n-\t\t\t\t\t io_val | LPI_GPIO_VALUE_OUT_MASK);\n+\t\t\t\tret = lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,\n+\t\t\t\t\t\t io_val | LPI_GPIO_VALUE_OUT_MASK);\n \t\t} else {\n \t\t\tif (io_val & LPI_GPIO_VALUE_OUT_MASK)\n-\t\t\t\tlpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,\n-\t\t\t\t\t io_val & ~LPI_GPIO_VALUE_OUT_MASK);\n+\t\t\t\tret = lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,\n+\t\t\t\t\t\t io_val & ~LPI_GPIO_VALUE_OUT_MASK);\n \t\t}\n \t}\n \n \tu32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);\n-\tlpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);\n+\tret = lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);\n+\n+out_unlock:\n \tmutex_unlock(&pctrl->lock);\n \n-\treturn 0;\n+\treturn ret;\n }\n \n static const struct pinmux_ops lpi_gpio_pinmux_ops = {\n@@ -165,8 +176,11 @@ static int lpi_config_get(struct pinctrl_dev *pctldev,\n \tint is_out;\n \tint pull;\n \tu32 ctl_reg;\n+\tint ret;\n \n-\tctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);\n+\tret = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg);\n+\tif (ret)\n+\t\treturn ret;\n \tis_out = ctl_reg & LPI_GPIO_OE_MASK;\n \tpull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);\n \n@@ -293,17 +307,22 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,\n \t}\n \n \tmutex_lock(&pctrl->lock);\n-\tval = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);\n+\tret = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG, &val);\n+\tif (ret) {\n+\t\tmutex_unlock(&pctrl->lock);\n+\t\tgoto out_unlock;\n+\t}\n \n \tu32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);\n \tu32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),\n \t\t\t LPI_GPIO_OUT_STRENGTH_MASK);\n \tu32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);\n \n-\tlpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);\n-\tmutex_unlock(&pctrl->lock);\n+\tret = lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);\n \n-\treturn 0;\n+out_unlock:\n+\tmutex_unlock(&pctrl->lock);\n+\treturn ret;\n }\n \n static const struct pinconf_ops lpi_gpio_pinconf_ops = {\n@@ -352,9 +371,13 @@ static int lpi_gpio_direction_output(struct gpio_chip *chip,\n static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)\n {\n \tstruct lpi_pinctrl *state = gpiochip_get_data(chip);\n+\tu32 val;\n+\tint ret;\n \n-\treturn lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &\n-\t\tLPI_GPIO_VALUE_IN_MASK;\n+\tret = lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\treturn val & LPI_GPIO_VALUE_IN_MASK;\n }\n \n static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)\n@@ -387,6 +410,7 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s,\n \tint drive;\n \tint pull;\n \tu32 ctl_reg;\n+\tint ret;\n \n \tstatic const char * const pulls[] = {\n \t\t\"no pull\",\n@@ -397,7 +421,11 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s,\n \n \tpctldev = pctldev ? : state->ctrl;\n \tpindesc = pctldev->desc->pins[offset];\n-\tctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);\n+\tret = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg);\n+\tif (ret) {\n+\t\tseq_printf(s, \" %-8s: \", pindesc.name, ret);\n+\t\treturn;\n+\t}\n \tis_out = ctl_reg & LPI_GPIO_OE_MASK;\n \n \tfunc = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);\n","prefixes":["v1","2/3"]}