{"id":2222665,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222665/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260413-casey-qcom-geni-rpmh-fixes-v1-1-2a83a67ac0f1@linaro.org/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260413-casey-qcom-geni-rpmh-fixes-v1-1-2a83a67ac0f1@linaro.org>","date":"2026-04-13T11:06:14","name":"[1/3] soc/qcom: rpmh: properly fix synchronous requests","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ef65cec17ad107e410cf504b0148ad0b681b7682","submitter":{"id":90679,"url":"http://patchwork.ozlabs.org/api/1.1/people/90679/?format=json","name":"Casey Connolly","email":"casey.connolly@linaro.org"},"delegate":{"id":151538,"url":"http://patchwork.ozlabs.org/api/1.1/users/151538/?format=json","username":"kcxt","first_name":"Casey","last_name":"Connolly","email":"casey.connolly@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260413-casey-qcom-geni-rpmh-fixes-v1-1-2a83a67ac0f1@linaro.org/mbox/","series":[{"id":499682,"url":"http://patchwork.ozlabs.org/api/1.1/series/499682/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499682","date":"2026-04-13T11:06:13","name":"Qualcomm: rpmh and regulator fixes","version":1,"mbox":"http://patchwork.ozlabs.org/series/499682/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222665/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222665/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=jueXWVoD;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260413-casey-qcom-geni-rpmh-fixes-v1-1-2a83a67ac0f1@linaro.org>","References":"<20260413-casey-qcom-geni-rpmh-fixes-v1-0-2a83a67ac0f1@linaro.org>","In-Reply-To":"\n <20260413-casey-qcom-geni-rpmh-fixes-v1-0-2a83a67ac0f1@linaro.org>","To":"Sumit Garg , u-boot-qcom@groups.io,\n u-boot@lists.denx.de","Cc":"Casey Connolly ,\n Neil Armstrong , Tom Rini ,\n Jaehoon Chung , Peng Fan ,\n Aswin Murugan ","X-Mailer":"b4 0.15-dev-47773","X-Developer-Signature":"v=1; a=openpgp-sha256; l=7252;\n i=casey.connolly@linaro.org; h=from:subject:message-id;\n bh=1kD/9o8ilNvnjXAiRilyTKcZatQVc2MxVZsGbSJ6HfQ=;\n b=owGbwMvMwCFYaeA6f6eBkTjjabUkhsw759RE32b4VJZcM6x5LiBxcNGEc6L+QiHXvvmahIqt/\n eBUN+drRykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZjIj9+MDPO/eesdXl5xaquI\n 9uZVLsUvLh4umJ3HbFQ8cY1N3JZHSzgZ/qmfm9do0HllzpaQ1XP0IlX/Trf48GL9ilVB6kr1/1c\n usa0CAA==","X-Developer-Key":"i=casey.connolly@linaro.org; a=openpgp;\n fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"We only ever use a single TCS group and it's always AMC. Disabling AMC\nimmediately after triggering the TCS group might be contributing to some\nof the issues we hit, so let's just defer cleaning things up until just\nbefore we boot the OS. The CMD_ENABLE register is cleared for every rpmh\ntransation to only select the appropriate commands, and it seems like we\ndon't need to unset the trigger bit for an AMC either.\n\nSigned-off-by: Casey Connolly \n---\n drivers/soc/qcom/rpmh-rsc.c | 70 ++++++++++++++++++++++++++++++++++-----------\n 1 file changed, 53 insertions(+), 17 deletions(-)","diff":"diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c\nindex 0b821cc6f9d8..5bf54429e793 100644\n--- a/drivers/soc/qcom/rpmh-rsc.c\n+++ b/drivers/soc/qcom/rpmh-rsc.c\n@@ -293,9 +293,9 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id,\n \n \tif (msg->wait_for_compl)\n \t\tcmd_msgid |= CMD_MSGID_RESP_REQ;\n \n-\tcmd_complete = read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_WAIT_FOR_CMPL], tcs_id);\n+\tcmd_complete = 0; //read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_WAIT_FOR_CMPL], tcs_id);\n \n \tfor (i = 0, j = cmd_id; i < msg->num_cmds; i++, j++) {\n \t\tcmd = &msg->cmds[i];\n \t\tcmd_enable |= BIT(j);\n@@ -306,17 +306,20 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id,\n \t\twrite_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_MSGID], tcs_id, j, msgid);\n \t\twrite_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], tcs_id, j, cmd->addr);\n \t\tif (!msg->is_read)\n \t\t\twrite_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_DATA], tcs_id, j, cmd->data);\n-\t\tdebug(\"tcs(%d): [%s] cmd_id: %d: msgid: %#x addr: %#x data: %#x complete: %#x\\n\",\n+\t\tdebug(\"tcs(%d): [%s] cmd_id: %d: msgid: %#x addr: %#x data: %#x read: %d\\n\",\n \t\t tcs_id, msg->state == RPMH_ACTIVE_ONLY_STATE ? \"active\" : \"?\", j, msgid,\n-\t\t cmd->addr, cmd->data, cmd_complete);\n+\t\t cmd->addr, cmd->data, msg->is_read);\n \t}\n \n-\tcmd_enable |= read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id);\n \twrite_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id, cmd_enable);\n \t/* U-Boot: Tell the DRV to wait for completion (?) so we can poll on DRV_STATUS */\n \t/* This register applies to the entire TCS group not per command */\n+\t/*\n+\t * FIXME: this seems to rather be a way to impose ordering on commands when multiple are\n+\t * sent in a single TCS request, needs more testing.\n+\t */\n \twrite_tcs_reg(drv, drv->regs[RSC_DRV_CMD_WAIT_FOR_CMPL], tcs_id, cmd_complete);\n }\n \n /**\n@@ -343,15 +346,14 @@ static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger)\n \n \t/*\n \t * HW req: Clear the DRV_CONTROL and enable TCS again\n \t * While clearing ensure that the AMC mode trigger is cleared\n-\t * and then the mode enable is cleared.\n+\t * U-Boot: keep AMC_MODE_ENABLE flag since clearing it might be\n+\t * interrupting in-flight commands.\n \t */\n \tenable = read_tcs_reg(drv, reg, tcs_id);\n \tenable &= ~TCS_AMC_MODE_TRIGGER;\n \twrite_tcs_reg_sync(drv, reg, tcs_id, enable);\n-\tenable &= ~TCS_AMC_MODE_ENABLE;\n-\twrite_tcs_reg_sync(drv, reg, tcs_id, enable);\n \n \tif (trigger) {\n \t\t/* Enable the AMC mode on the TCS and then trigger the TCS */\n \t\tenable = TCS_AMC_MODE_ENABLE;\n@@ -387,12 +389,13 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg)\n {\n \tstruct tcs_group *tcs;\n \tint tcs_id, i = 0;\n \tu32 val;\n+\tu32 addr;\n \n \ttcs = get_tcs_for_msg(drv, msg);\n-\tif (IS_ERR_OR_NULL(tcs))\n-\t\treturn 0;\n+\tif (IS_ERR(tcs))\n+\t\treturn PTR_ERR(tcs);\n \n \t/* U-Boot is single-threaded, always use the first TCS as we'll never conflict */\n \ttcs_id = tcs->offset;\n \tif (!read_tcs_reg(drv, drv->regs[RSC_DRV_STATUS], tcs_id)) {\n@@ -400,9 +403,8 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg)\n \t\treturn -EBUSY;\n \t}\n \n \ttcs->req[tcs_id - tcs->offset] = msg;\n-\tgeneric_set_bit(tcs_id, drv->tcs_in_use);\n \n \t/*\n \t * These two can be done after the lock is released because:\n \t * - We marked \"tcs_in_use\" under lock.\n@@ -413,28 +415,35 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg)\n \t */\n \t__tcs_buffer_write(drv, tcs_id, 0, msg);\n \t__tcs_set_trigger(drv, tcs_id, true);\n \n-\t/* U-Boot: Now wait for the TCS to be cleared, indicating that we're done. */\n+\t/*\n+\t * U-Boot: Now wait for the status done flag and for the TCS to be cleared.\n+\t * Just waiting for one of these isn't always enough. On reads we have to wait for\n+\t * the status register to indicate that the response data is ready.\n+\t */\n+\tfor (i = 0; i < USEC_PER_SEC; i++) {\n+\t\taddr = readl_relaxed(drv->tcs_base + drv->regs[RSC_DRV_IRQ_STATUS]);\n+\t\tif (addr & BIT(tcs_id))\n+\t\t\tbreak;\n+\t\tudelay(1);\n+\t}\n+\n \tfor (i = 0; i < USEC_PER_SEC; i++) {\n \t\tval = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_STATUS], tcs_id, 0);\n \t\tif (val & CMD_STATUS_COMPL)\n \t\t\tbreak;\n \t\tudelay(1);\n \t}\n \n-\t/* U-Boot: read the response now we know it's available */\n+\t/* U-Boot: read the response when it becomes available */\n \tif (msg->is_read) {\n \t\tmsg->cmds[0].data = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_RESP_DATA], tcs_id, 0);\n \t\tlog_debug(\"data response: %#x\\n\", msg->cmds[0].data);\n \t}\n \n \t__tcs_set_trigger(drv, tcs_id, false);\n-\n-\t/* Reclaim the TCS */\n-\twrite_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id, 0);\n \twritel_relaxed(BIT(tcs_id), drv->tcs_base + drv->regs[RSC_DRV_IRQ_CLEAR]);\n-\tgeneric_clear_bit(tcs_id, drv->tcs_in_use);\n \n \tif (i == USEC_PER_SEC) {\n \t\tlog_err(\"%s: error writing %#x to %d:%#x\\n\", drv->name,\n \t\t\tmsg->cmds[0].addr, tcs_id, drv->regs[RSC_DRV_CMD_ADDR]);\n@@ -563,8 +572,34 @@ static int rpmh_rsc_probe(struct udevice *dev)\n \n \treturn ret;\n }\n \n+static int rpmh_rsc_remove(struct udevice *dev)\n+{\n+\tstruct rsc_drv *drv = dev_get_priv(dev);\n+\tstruct tcs_group *tcs = &drv->tcs[ACTIVE_TCS];\n+\tu32 tcs_id = tcs->offset;\n+\n+\tfor (int i = 0; i < 10 && !read_tcs_reg(drv, drv->regs[RSC_DRV_STATUS], tcs_id); i++) {\n+\t\tif (i == 0)\n+\t\t\tprintf(\"Waiting for TCS %d to be free...\\n\", tcs_id);\n+\t\tudelay(100);\n+\t}\n+\n+\t/* Clean up for the OS! */\n+\twrite_tcs_reg(drv, drv->regs[RSC_DRV_CMD_WAIT_FOR_CMPL], tcs_id, 0);\n+\n+\t/* Clear the AMC enable bit for all TCS commands we used */\n+\twrite_tcs_reg_sync(drv, drv->regs[RSC_DRV_CONTROL], tcs_id, 0);\n+\t/* Disable all commands for the single AMC we used */\n+\twrite_tcs_reg_sync(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id, 0);\n+\n+\t/* Make sure IRQs are all clear too */\n+\twritel_relaxed(tcs->mask, drv->tcs_base + drv->regs[RSC_DRV_IRQ_CLEAR]);\n+\n+\treturn 0;\n+}\n+\n static const struct udevice_id qcom_rpmh_ids[] = {\n \t{ .compatible = \"qcom,rpmh-rsc\" },\n \t{ }\n };\n@@ -573,11 +608,12 @@ U_BOOT_DRIVER(qcom_rpmh_rsc) = {\n \t.name\t\t= \"qcom_rpmh_rsc\",\n \t.id\t\t= UCLASS_MISC,\n \t.priv_auto\t= sizeof(struct rsc_drv),\n \t.probe\t\t= rpmh_rsc_probe,\n+\t.remove\t\t= rpmh_rsc_remove,\n \t.of_match\t= qcom_rpmh_ids,\n \t/* rpmh is under CLUSTER_PD which we don't support, so skip trying to enable PDs */\n-\t.flags\t\t= DM_FLAG_DEFAULT_PD_CTRL_OFF,\n+\t.flags\t\t= DM_FLAG_DEFAULT_PD_CTRL_OFF | DM_FLAG_OS_PREPARE,\n };\n \n MODULE_DESCRIPTION(\"Qualcomm Technologies, Inc. RPMh Driver\");\n MODULE_LICENSE(\"GPL v2\");\n","prefixes":["1/3"]}