{"id":2222659,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222659/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413102326.59343-2-dev-josejavier.rodriguez@duagon.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413102326.59343-2-dev-josejavier.rodriguez@duagon.com>","date":"2026-04-13T10:23:24","name":"[RFC,v2,1/3] gpio: mmio: convert accessors to generic register descriptors","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a44cb983f527175e89cc04d739086065fa24a551","submitter":{"id":92011,"url":"http://patchwork.ozlabs.org/api/1.1/people/92011/?format=json","name":"Jose Javier Rodriguez Barbarin","email":"dev-josejavier.rodriguez@duagon.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413102326.59343-2-dev-josejavier.rodriguez@duagon.com/mbox/","series":[{"id":499676,"url":"http://patchwork.ozlabs.org/api/1.1/series/499676/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499676","date":"2026-04-13T10:23:25","name":"gpio: add PMIO support to gpio-mmio","version":2,"mbox":"http://patchwork.ozlabs.org/series/499676/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222659/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222659/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=duagon.com header.i=@duagon.com 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Apr 2026 10:24:12.9859\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 56172a57-2292-4b17-eafe-08de9946cee1","X-MS-Exchange-CrossTenant-Id":"e5e7e96e-8a28-45d6-9093-a40dd5b51a57","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=e5e7e96e-8a28-45d6-9093-a40dd5b51a57;Ip=[2a01:4f8:272:5fe6::218];Helo=[hz-deliver02.de.seppmail.cloud]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tDU2PEPF0001E9C2.eurprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem"},"content":"Convert the gpio-mmio accessors to use union gpio_chip_reg instead of\nthe previous MMIO-only register type.\n\nThis allows the same accessors to operate on both MMIO and PMIO\nregisters and aligns gpio-mmio with the updated gpio_generic_chip API.\n\nMove the initialization code shared by MMIO and PMIO devices to a new\nfunction gpio_generic_chip_init_common(), leaving gpio_generic_chip_init()\nwith the MMIO-specific initialization.\n\nSigned-off-by: Jose Javier Rodriguez Barbarin \n---\n drivers/gpio/gpio-mmio.c | 208 ++++++++++++++++++-----------------\n include/linux/gpio/generic.h | 37 +++++--\n 2 files changed, 138 insertions(+), 107 deletions(-)","diff":"diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c\nindex edbcaad57d00..39326ab7e494 100644\n--- a/drivers/gpio/gpio-mmio.c\n+++ b/drivers/gpio/gpio-mmio.c\n@@ -62,66 +62,71 @@ o ` ~~~~\\___/~~~~ ` controller in FPGA is ,.`\n \n #include \"gpiolib.h\"\n \n-static void gpio_mmio_write8(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write8(union gpio_chip_reg *reg, unsigned long data)\n {\n-\twriteb(data, reg);\n+\twriteb(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read8(void __iomem *reg)\n+static unsigned long gpio_mmio_read8(union gpio_chip_reg *reg)\n {\n-\treturn readb(reg);\n+\treturn readb(reg->mmio);\n }\n \n-static void gpio_mmio_write16(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write16(union gpio_chip_reg *reg, unsigned long data)\n {\n-\twritew(data, reg);\n+\twritew(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read16(void __iomem *reg)\n+static unsigned long gpio_mmio_read16(union gpio_chip_reg *reg)\n {\n-\treturn readw(reg);\n+\treturn readw(reg->mmio);\n }\n \n-static void gpio_mmio_write32(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write32(union gpio_chip_reg *reg, unsigned long data)\n {\n-\twritel(data, reg);\n+\twritel(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read32(void __iomem *reg)\n+static unsigned long gpio_mmio_read32(union gpio_chip_reg *reg)\n {\n-\treturn readl(reg);\n+\treturn readl(reg->mmio);\n }\n \n #if BITS_PER_LONG >= 64\n-static void gpio_mmio_write64(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write64(union gpio_chip_reg *reg, unsigned long data)\n {\n-\twriteq(data, reg);\n+\twriteq(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read64(void __iomem *reg)\n+static unsigned long gpio_mmio_read64(union gpio_chip_reg *reg)\n {\n-\treturn readq(reg);\n+\treturn readq(reg->mmio);\n }\n #endif /* BITS_PER_LONG >= 64 */\n \n-static void gpio_mmio_write16be(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write16be(union gpio_chip_reg *reg, unsigned long data)\n {\n-\tiowrite16be(data, reg);\n+\tiowrite16be(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read16be(void __iomem *reg)\n+static unsigned long gpio_mmio_read16be(union gpio_chip_reg *reg)\n {\n-\treturn ioread16be(reg);\n+\treturn ioread16be(reg->mmio);\n }\n \n-static void gpio_mmio_write32be(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write32be(union gpio_chip_reg *reg, unsigned long data)\n {\n-\tiowrite32be(data, reg);\n+\tiowrite32be(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read32be(void __iomem *reg)\n+static unsigned long gpio_mmio_read32be(union gpio_chip_reg *reg)\n {\n-\treturn ioread32be(reg);\n+\treturn ioread32be(reg->mmio);\n+}\n+\n+static inline bool gpio_chip_reg_is_set(union gpio_chip_reg *reg)\n+{\n+\treturn reg->port != 0;\n }\n \n static unsigned long gpio_mmio_line2mask(struct gpio_chip *gc, unsigned int line)\n@@ -140,9 +145,9 @@ static int gpio_mmio_get_set(struct gpio_chip *gc, unsigned int gpio)\n \tbool dir = !!(chip->sdir & pinmask);\n \n \tif (dir)\n-\t\treturn !!(chip->read_reg(chip->reg_set) & pinmask);\n+\t\treturn !!(chip->read_reg(&chip->reg_set) & pinmask);\n \n-\treturn !!(chip->read_reg(chip->reg_dat) & pinmask);\n+\treturn !!(chip->read_reg(&chip->reg_dat) & pinmask);\n }\n \n /*\n@@ -162,9 +167,9 @@ static int gpio_mmio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,\n \tget_mask = *mask & ~chip->sdir;\n \n \tif (set_mask)\n-\t\t*bits |= chip->read_reg(chip->reg_set) & set_mask;\n+\t\t*bits |= chip->read_reg(&chip->reg_set) & set_mask;\n \tif (get_mask)\n-\t\t*bits |= chip->read_reg(chip->reg_dat) & get_mask;\n+\t\t*bits |= chip->read_reg(&chip->reg_dat) & get_mask;\n \n \treturn 0;\n }\n@@ -173,7 +178,7 @@ static int gpio_mmio_get(struct gpio_chip *gc, unsigned int gpio)\n {\n \tstruct gpio_generic_chip *chip = to_gpio_generic_chip(gc);\n \n-\treturn !!(chip->read_reg(chip->reg_dat) & gpio_mmio_line2mask(gc, gpio));\n+\treturn !!(chip->read_reg(&chip->reg_dat) & gpio_mmio_line2mask(gc, gpio));\n }\n \n /*\n@@ -186,7 +191,7 @@ static int gpio_mmio_get_multiple(struct gpio_chip *gc, unsigned long *mask,\n \n \t/* Make sure we first clear any bits that are zero when we read the register */\n \t*bits &= ~*mask;\n-\t*bits |= chip->read_reg(chip->reg_dat) & *mask;\n+\t*bits |= chip->read_reg(&chip->reg_dat) & *mask;\n \treturn 0;\n }\n \n@@ -209,7 +214,7 @@ static int gpio_mmio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,\n \t\treadmask |= gpio_mmio_line2mask(gc, bit);\n \n \t/* Read the register */\n-\tval = chip->read_reg(chip->reg_dat) & readmask;\n+\tval = chip->read_reg(&chip->reg_dat) & readmask;\n \n \t/*\n \t * Mirror the result into the \"bits\" result, this will give line 0\n@@ -238,7 +243,7 @@ static int gpio_mmio_set(struct gpio_chip *gc, unsigned int gpio, int val)\n \telse\n \t\tchip->sdata &= ~mask;\n \n-\tchip->write_reg(chip->reg_dat, chip->sdata);\n+\tchip->write_reg(&chip->reg_dat, chip->sdata);\n \n \treturn 0;\n }\n@@ -250,9 +255,9 @@ static int gpio_mmio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,\n \tunsigned long mask = gpio_mmio_line2mask(gc, gpio);\n \n \tif (val)\n-\t\tchip->write_reg(chip->reg_set, mask);\n+\t\tchip->write_reg(&chip->reg_set, mask);\n \telse\n-\t\tchip->write_reg(chip->reg_clr, mask);\n+\t\tchip->write_reg(&chip->reg_clr, mask);\n \n \treturn 0;\n }\n@@ -269,7 +274,7 @@ static int gpio_mmio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)\n \telse\n \t\tchip->sdata &= ~mask;\n \n-\tchip->write_reg(chip->reg_set, chip->sdata);\n+\tchip->write_reg(&chip->reg_set, chip->sdata);\n \n \treturn 0;\n }\n@@ -297,7 +302,7 @@ static void gpio_mmio_multiple_get_masks(struct gpio_chip *gc,\n static void gpio_mmio_set_multiple_single_reg(struct gpio_chip *gc,\n \t\t\t\t\t unsigned long *mask,\n \t\t\t\t\t unsigned long *bits,\n-\t\t\t\t\t void __iomem *reg)\n+\t\t\t\t\t union gpio_chip_reg *reg)\n {\n \tstruct gpio_generic_chip *chip = to_gpio_generic_chip(gc);\n \tunsigned long set_mask, clear_mask;\n@@ -317,7 +322,7 @@ static int gpio_mmio_set_multiple(struct gpio_chip *gc, unsigned long *mask,\n {\n \tstruct gpio_generic_chip *chip = to_gpio_generic_chip(gc);\n \n-\tgpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat);\n+\tgpio_mmio_set_multiple_single_reg(gc, mask, bits, &chip->reg_dat);\n \n \treturn 0;\n }\n@@ -327,7 +332,7 @@ static int gpio_mmio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,\n {\n \tstruct gpio_generic_chip *chip = to_gpio_generic_chip(gc);\n \n-\tgpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_set);\n+\tgpio_mmio_set_multiple_single_reg(gc, mask, bits, &chip->reg_set);\n \n \treturn 0;\n }\n@@ -342,9 +347,9 @@ static int gpio_mmio_set_multiple_with_clear(struct gpio_chip *gc,\n \tgpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);\n \n \tif (set_mask)\n-\t\tchip->write_reg(chip->reg_set, set_mask);\n+\t\tchip->write_reg(&chip->reg_set, set_mask);\n \tif (clear_mask)\n-\t\tchip->write_reg(chip->reg_clr, clear_mask);\n+\t\tchip->write_reg(&chip->reg_clr, clear_mask);\n \n \treturn 0;\n }\n@@ -394,10 +399,10 @@ static int gpio_mmio_dir_in(struct gpio_chip *gc, unsigned int gpio)\n \tscoped_guard(raw_spinlock_irqsave, &chip->lock) {\n \t\tchip->sdir &= ~gpio_mmio_line2mask(gc, gpio);\n \n-\t\tif (chip->reg_dir_in)\n-\t\t\tchip->write_reg(chip->reg_dir_in, ~chip->sdir);\n-\t\tif (chip->reg_dir_out)\n-\t\t\tchip->write_reg(chip->reg_dir_out, chip->sdir);\n+\t\tif (gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\t\tchip->write_reg(&chip->reg_dir_in, ~chip->sdir);\n+\t\tif (gpio_chip_reg_is_set(&chip->reg_dir_out))\n+\t\t\tchip->write_reg(&chip->reg_dir_out, chip->sdir);\n \t}\n \n \treturn gpio_mmio_dir_return(gc, gpio, false);\n@@ -414,14 +419,14 @@ static int gpio_mmio_get_dir(struct gpio_chip *gc, unsigned int gpio)\n \t\treturn GPIO_LINE_DIRECTION_IN;\n \t}\n \n-\tif (chip->reg_dir_out) {\n-\t\tif (chip->read_reg(chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio))\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_out)) {\n+\t\tif (chip->read_reg(&chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio))\n \t\t\treturn GPIO_LINE_DIRECTION_OUT;\n \t\treturn GPIO_LINE_DIRECTION_IN;\n \t}\n \n-\tif (chip->reg_dir_in)\n-\t\tif (!(chip->read_reg(chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio)))\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\tif (!(chip->read_reg(&chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio)))\n \t\t\treturn GPIO_LINE_DIRECTION_OUT;\n \n \treturn GPIO_LINE_DIRECTION_IN;\n@@ -435,10 +440,10 @@ static void gpio_mmio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)\n \n \tchip->sdir |= gpio_mmio_line2mask(gc, gpio);\n \n-\tif (chip->reg_dir_in)\n-\t\tchip->write_reg(chip->reg_dir_in, ~chip->sdir);\n-\tif (chip->reg_dir_out)\n-\t\tchip->write_reg(chip->reg_dir_out, chip->sdir);\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\tchip->write_reg(&chip->reg_dir_in, ~chip->sdir);\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_out))\n+\t\tchip->write_reg(&chip->reg_dir_out, chip->sdir);\n }\n \n static int gpio_mmio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,\n@@ -526,25 +531,22 @@ static int gpio_mmio_setup_accessors(struct device *dev,\n *\t- an input direction register (named \"dirin\") where a 1 bit indicates\n *\tthe GPIO is an input.\n */\n-static int gpio_mmio_setup_io(struct gpio_generic_chip *chip,\n-\t\t\t const struct gpio_generic_chip_config *cfg)\n+static int gpio_mmio_setup_io(struct gpio_generic_chip *chip, int flags)\n {\n \tstruct gpio_chip *gc = &chip->gc;\n \n-\tchip->reg_dat = cfg->dat;\n-\tif (!chip->reg_dat)\n+\tif (!gpio_chip_reg_is_set(&chip->reg_dat))\n \t\treturn -EINVAL;\n \n-\tif (cfg->set && cfg->clr) {\n-\t\tchip->reg_set = cfg->set;\n-\t\tchip->reg_clr = cfg->clr;\n+\tif (gpio_chip_reg_is_set(&chip->reg_set) &&\n+\t gpio_chip_reg_is_set(&chip->reg_clr)) {\n \t\tgc->set = gpio_mmio_set_with_clear;\n \t\tgc->set_multiple = gpio_mmio_set_multiple_with_clear;\n-\t} else if (cfg->set && !cfg->clr) {\n-\t\tchip->reg_set = cfg->set;\n+\t} else if (gpio_chip_reg_is_set(&chip->reg_set) &&\n+\t\t !gpio_chip_reg_is_set(&chip->reg_clr)) {\n \t\tgc->set = gpio_mmio_set_set;\n \t\tgc->set_multiple = gpio_mmio_set_multiple_set;\n-\t} else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) {\n+\t} else if (flags & GPIO_GENERIC_NO_OUTPUT) {\n \t\tgc->set = gpio_mmio_set_none;\n \t\tgc->set_multiple = NULL;\n \t} else {\n@@ -552,8 +554,8 @@ static int gpio_mmio_setup_io(struct gpio_generic_chip *chip,\n \t\tgc->set_multiple = gpio_mmio_set_multiple;\n \t}\n \n-\tif (!(cfg->flags & GPIO_GENERIC_UNREADABLE_REG_SET) &&\n-\t (cfg->flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) {\n+\tif (!(flags & GPIO_GENERIC_UNREADABLE_REG_SET) &&\n+\t (flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) {\n \t\tgc->get = gpio_mmio_get_set;\n \t\tif (!chip->be_bits)\n \t\t\tgc->get_multiple = gpio_mmio_get_set_multiple;\n@@ -575,27 +577,24 @@ static int gpio_mmio_setup_io(struct gpio_generic_chip *chip,\n \treturn 0;\n }\n \n-static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip,\n-\t\t\t\t const struct gpio_generic_chip_config *cfg)\n+static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip, int flags)\n {\n \tstruct gpio_chip *gc = &chip->gc;\n-\n-\tif (cfg->dirout || cfg->dirin) {\n-\t\tchip->reg_dir_out = cfg->dirout;\n-\t\tchip->reg_dir_in = cfg->dirin;\n-\t\tif (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT)\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_out) ||\n+\t\tgpio_chip_reg_is_set(&chip->reg_dir_in)) {\n+\t\tif (flags & GPIO_GENERIC_NO_SET_ON_INPUT)\n \t\t\tgc->direction_output = gpio_mmio_dir_out_dir_first;\n \t\telse\n \t\t\tgc->direction_output = gpio_mmio_dir_out_val_first;\n \t\tgc->direction_input = gpio_mmio_dir_in;\n \t\tgc->get_direction = gpio_mmio_get_dir;\n \t} else {\n-\t\tif (cfg->flags & GPIO_GENERIC_NO_OUTPUT)\n+\t\tif (flags & GPIO_GENERIC_NO_OUTPUT)\n \t\t\tgc->direction_output = gpio_mmio_dir_out_err;\n \t\telse\n \t\t\tgc->direction_output = gpio_mmio_simple_dir_out;\n \n-\t\tif (cfg->flags & GPIO_GENERIC_NO_INPUT)\n+\t\tif (flags & GPIO_GENERIC_NO_INPUT)\n \t\t\tgc->direction_input = gpio_mmio_dir_in_err;\n \t\telse\n \t\t\tgc->direction_input = gpio_mmio_simple_dir_in;\n@@ -617,25 +616,18 @@ static int gpio_mmio_request(struct gpio_chip *gc, unsigned int gpio_pin)\n \treturn 0;\n }\n \n-/**\n- * gpio_generic_chip_init() - Initialize a generic GPIO chip.\n- * @chip: Generic GPIO chip to set up.\n- * @cfg: Generic GPIO chip configuration.\n- *\n- * Returns 0 on success, negative error number on failure.\n- */\n-int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n-\t\t\t const struct gpio_generic_chip_config *cfg)\n+static int gpio_generic_chip_init_common(struct gpio_generic_chip *chip,\n+\t\t\t\t\tint sz,\n+\t\t\t\t\tint flags,\n+\t\t\t\t\tstruct device *dev)\n {\n \tstruct gpio_chip *gc = &chip->gc;\n-\tunsigned long flags = cfg->flags;\n-\tstruct device *dev = cfg->dev;\n \tint ret;\n \n-\tif (!is_power_of_2(cfg->sz))\n+\tif (!is_power_of_2(sz))\n \t\treturn -EINVAL;\n \n-\tchip->bits = cfg->sz * 8;\n+\tchip->bits = sz * 8;\n \tif (chip->bits > BITS_PER_LONG)\n \t\treturn -EINVAL;\n \n@@ -650,16 +642,16 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n \tif (ret)\n \t\tgc->ngpio = chip->bits;\n \n-\tret = gpio_mmio_setup_io(chip, cfg);\n+\tret = gpio_mmio_setup_io(chip, flags);\n \tif (ret)\n \t\treturn ret;\n \n \tret = gpio_mmio_setup_accessors(dev, chip,\n-\t\t\t\t flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);\n+\t\t\t\tflags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);\n \tif (ret)\n \t\treturn ret;\n \n-\tret = gpio_mmio_setup_direction(chip, cfg);\n+\tret = gpio_mmio_setup_direction(chip, flags);\n \tif (ret)\n \t\treturn ret;\n \n@@ -669,10 +661,10 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n \t\tgc->free = gpiochip_generic_free;\n \t}\n \n-\tchip->sdata = chip->read_reg(chip->reg_dat);\n+\tchip->sdata = chip->read_reg(&chip->reg_dat);\n \tif (gc->set == gpio_mmio_set_set &&\n \t\t\t!(flags & GPIO_GENERIC_UNREADABLE_REG_SET))\n-\t\tchip->sdata = chip->read_reg(chip->reg_set);\n+\t\tchip->sdata = chip->read_reg(&chip->reg_set);\n \n \tif (flags & GPIO_GENERIC_UNREADABLE_REG_DIR)\n \t\tchip->dir_unreadable = true;\n@@ -680,24 +672,44 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n \t/*\n \t * Inspect hardware to find initial direction setting.\n \t */\n-\tif ((chip->reg_dir_out || chip->reg_dir_in) &&\n+\tif ((gpio_chip_reg_is_set(&chip->reg_dir_out) || gpio_chip_reg_is_set(&chip->reg_dir_in)) &&\n \t !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) {\n-\t\tif (chip->reg_dir_out)\n-\t\t\tchip->sdir = chip->read_reg(chip->reg_dir_out);\n-\t\telse if (chip->reg_dir_in)\n-\t\t\tchip->sdir = ~chip->read_reg(chip->reg_dir_in);\n+\t\tif (gpio_chip_reg_is_set(&chip->reg_dir_out))\n+\t\t\tchip->sdir = chip->read_reg(&chip->reg_dir_out);\n+\t\telse if (gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\t\tchip->sdir = ~chip->read_reg(&chip->reg_dir_in);\n \t\t/*\n \t\t * If we have two direction registers, synchronise\n \t\t * input setting to output setting, the library\n \t\t * can not handle a line being input and output at\n \t\t * the same time.\n \t\t */\n-\t\tif (chip->reg_dir_out && chip->reg_dir_in)\n-\t\t\tchip->write_reg(chip->reg_dir_in, ~chip->sdir);\n+\t\tif (gpio_chip_reg_is_set(&chip->reg_dir_out) &&\n+\t\t gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\t\tchip->write_reg(&chip->reg_dir_in, ~chip->sdir);\n \t}\n \n \treturn ret;\n }\n+\n+/**\n+ * gpio_generic_chip_init() - Initialize a generic GPIO chip\n+ * @chip: Generic GPIO chip to set up.\n+ * @cfg: Generic GPIO chip configuration.\n+ *\n+ * Returns 0 on success, negative error number on failure.\n+ */\n+int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n+\t\t\t const struct gpio_generic_chip_config *cfg)\n+{\n+\tchip->reg_dat.mmio = cfg->dat;\n+\tchip->reg_set.mmio = cfg->set;\n+\tchip->reg_clr.mmio = cfg->clr;\n+\tchip->reg_dir_in.mmio = cfg->dirin;\n+\tchip->reg_dir_out.mmio = cfg->dirout;\n+\n+\treturn gpio_generic_chip_init_common(chip, cfg->sz, cfg->flags, cfg->dev);\n+}\n EXPORT_SYMBOL_GPL(gpio_generic_chip_init);\n \n #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)\ndiff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h\nindex ff566dc9c3cb..30f0d87422e9 100644\n--- a/include/linux/gpio/generic.h\n+++ b/include/linux/gpio/generic.h\n@@ -56,6 +56,19 @@ struct gpio_generic_chip_config {\n \tunsigned long flags;\n };\n \n+/**\n+ * union gpio_chip_reg - Generic GPIO chip register descriptor for MMIO or port-mapped I/O\n+ * @mmio: MMIO register address.\n+ * @port: I/O Port register address.\n+ *\n+ * Describes a GPIO chip register located either in MMIO space or in\n+ * port-mapped I/O space.\n+ */\n+union gpio_chip_reg {\n+\tvoid __iomem *mmio;\n+\tunsigned long port;\n+};\n+\n /**\n * struct gpio_generic_chip - Generic GPIO chip implementation.\n * @gc: The underlying struct gpio_chip object, implementing low-level GPIO\n@@ -84,14 +97,14 @@ struct gpio_generic_chip_config {\n */\n struct gpio_generic_chip {\n \tstruct gpio_chip gc;\n-\tunsigned long (*read_reg)(void __iomem *reg);\n-\tvoid (*write_reg)(void __iomem *reg, unsigned long data);\n+\tunsigned long (*read_reg)(union gpio_chip_reg *reg);\n+\tvoid (*write_reg)(union gpio_chip_reg *reg, unsigned long data);\n \tbool be_bits;\n-\tvoid __iomem *reg_dat;\n-\tvoid __iomem *reg_set;\n-\tvoid __iomem *reg_clr;\n-\tvoid __iomem *reg_dir_out;\n-\tvoid __iomem *reg_dir_in;\n+\tunion gpio_chip_reg reg_dat;\n+\tunion gpio_chip_reg reg_set;\n+\tunion gpio_chip_reg reg_clr;\n+\tunion gpio_chip_reg reg_dir_out;\n+\tunion gpio_chip_reg reg_dir_in;\n \tbool dir_unreadable;\n \tbool pinctrl;\n \tint bits;\n@@ -143,10 +156,13 @@ gpio_generic_chip_set(struct gpio_generic_chip *chip, unsigned int offset,\n static inline unsigned long\n gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg)\n {\n+\tunion gpio_chip_reg rg;\n+\n \tif (WARN_ON(!chip->read_reg))\n \t\treturn 0;\n \n-\treturn chip->read_reg(reg);\n+\trg.mmio = reg;\n+\treturn chip->read_reg(&rg);\n }\n \n /**\n@@ -158,10 +174,13 @@ gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg)\n static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip,\n \t\t\t\t\t void __iomem *reg, unsigned long val)\n {\n+\tunion gpio_chip_reg rg;\n+\n \tif (WARN_ON(!chip->write_reg))\n \t\treturn;\n \n-\tchip->write_reg(reg, val);\n+\trg.mmio = reg;\n+\tchip->write_reg(&rg, val);\n }\n \n #define gpio_generic_chip_lock(gen_gc) \\\n","prefixes":["RFC","v2","1/3"]}