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Apr 2026 10:24:17.1816\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 5e455efd-4ba0-4f90-b922-08de9946d161","X-MS-Exchange-CrossTenant-Id":"e5e7e96e-8a28-45d6-9093-a40dd5b51a57","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=e5e7e96e-8a28-45d6-9093-a40dd5b51a57;Ip=[2a01:4f8:a0:13df::219];Helo=[hz-deliver01.de.seppmail.cloud]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tDU2PEPF0001E9C5.eurprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem"},"content":"Add a new structure gpio_generic_chip_port_config for configuring\nPMIO chips. A new function gpio_generic_chip_port_init() allows to\nconfigure them.\n\nAdd an io_port field to struct gpio_generic_chip to distinguish PMIO\nfrom MMIO chips during initialization and select the proper register\naccessors.\n\nSigned-off-by: Jose Javier Rodriguez Barbarin \n---\n drivers/gpio/gpio-mmio.c | 30 ++++++++++++++++++++++++--\n include/linux/gpio/generic.h | 41 ++++++++++++++++++++++++++++++++++++\n 2 files changed, 69 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c\nindex d23c5d275e6b..01e2afd8d6f1 100644\n--- a/drivers/gpio/gpio-mmio.c\n+++ b/drivers/gpio/gpio-mmio.c\n@@ -740,8 +740,12 @@ static int gpio_generic_chip_init_common(struct gpio_generic_chip *chip,\n \tif (ret)\n \t\treturn ret;\n \n-\tret = gpio_mmio_setup_accessors(dev, chip,\n-\t\t\t\tflags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);\n+\tif (chip->io_port)\n+\t\tret = gpio_port_setup_accessors(dev, chip,\n+\t\t\t\t\tflags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);\n+\telse\n+\t\tret = gpio_mmio_setup_accessors(dev, chip,\n+\t\t\t\t\tflags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);\n \tif (ret)\n \t\treturn ret;\n \n@@ -801,11 +805,33 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n \tchip->reg_clr.mmio = cfg->clr;\n \tchip->reg_dir_in.mmio = cfg->dirin;\n \tchip->reg_dir_out.mmio = cfg->dirout;\n+\tchip->io_port = true;\n \n \treturn gpio_generic_chip_init_common(chip, cfg->sz, cfg->flags, cfg->dev);\n }\n EXPORT_SYMBOL_GPL(gpio_generic_chip_init);\n \n+/**\n+ * gpio_generic_chip_port_init() - Initialize a generic GPIO chip for I/O port devices\n+ * @chip: Generic GPIO chip to set up.\n+ * @cfg: Generic GPIO chip configuration.\n+ *\n+ * Returns 0 on success, negative error number on failure.\n+ */\n+int gpio_generic_chip_port_init(struct gpio_generic_chip *chip,\n+\t\t\t const struct gpio_generic_chip_port_config *cfg)\n+{\n+\tchip->reg_dat.port = cfg->dat;\n+\tchip->reg_set.port = cfg->set;\n+\tchip->reg_clr.port = cfg->clr;\n+\tchip->reg_dir_in.port = cfg->dirin;\n+\tchip->reg_dir_out.port = cfg->dirout;\n+\tchip->io_port = true;\n+\n+\treturn gpio_generic_chip_init_common(chip, cfg->sz, cfg->flags, cfg->dev);\n+}\n+EXPORT_SYMBOL_GPL(gpio_generic_chip_port_init);\n+\n #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)\n \n static void __iomem *gpio_mmio_map(struct platform_device *pdev,\ndiff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h\nindex 30f0d87422e9..93ce5f09c0d3 100644\n--- a/include/linux/gpio/generic.h\n+++ b/include/linux/gpio/generic.h\n@@ -56,6 +56,43 @@ struct gpio_generic_chip_config {\n \tunsigned long flags;\n };\n \n+/**\n+ * struct gpio_generic_chip_port_config - Generic GPIO chip configuration data for I/O port devices\n+ * @dev: Parent device of the new GPIO chip (compulsory).\n+ * @sz: Size (width) of the PMIO registers in bytes, typically 1, 2 or 4.\n+ * @dat: PMIO address for the register to READ the value of the GPIO lines, it\n+ * is expected that a 1 in the corresponding bit in this register means\n+ * the line is asserted.\n+ * @set: PMIO address for the register to SET the value of the GPIO lines, it\n+ * is expected that we write the line with 1 in this register to drive\n+ * the GPIO line high.\n+ * @clr: PMIO address for the register to CLEAR the value of the GPIO lines,\n+ * it is expected that we write the line with 1 in this register to\n+ * drive the GPIO line low. It is allowed to leave this address as NULL,\n+ * in that case the SET register will be assumed to also clear the GPIO\n+ * lines, by actively writing the line with 0.\n+ * @dirout: PMIO address for the register to set the line as OUTPUT. It is\n+ * assumed that setting a line to 1 in this register will turn that\n+ * line into an output line. Conversely, setting the line to 0 will\n+ * turn that line into an input.\n+ * @dirin: PMIO address for the register to set this line as INPUT. It is\n+ * assumed that setting a line to 1 in this register will turn that\n+ * line into an input line. Conversely, setting the line to 0 will\n+ * turn that line into an output.\n+ * @flags: Different flags that will affect the behaviour of the device, such\n+ * as endianness etc.\n+ */\n+struct gpio_generic_chip_port_config {\n+\tstruct device *dev;\n+\tunsigned long sz;\n+\tunsigned long dat;\n+\tunsigned long set;\n+\tunsigned long clr;\n+\tunsigned long dirout;\n+\tunsigned long dirin;\n+\tunsigned long flags;\n+};\n+\n /**\n * union gpio_chip_reg - Generic GPIO chip register descriptor for MMIO or port-mapped I/O\n * @mmio: MMIO register address.\n@@ -79,6 +116,7 @@ union gpio_chip_reg {\n * representing line 0, bit 30 is line 1 ... bit 0 is line 31) this\n * is set to true by the generic GPIO core. It is for internal\n * housekeeping only.\n+ * @io_port: indicates that the device is I/O port-mapped\n * @reg_dat: data (in) register for generic GPIO\n * @reg_set: output set register (out=high) for generic GPIO\n * @reg_clr: output clear register (out=low) for generic GPIO\n@@ -100,6 +138,7 @@ struct gpio_generic_chip {\n \tunsigned long (*read_reg)(union gpio_chip_reg *reg);\n \tvoid (*write_reg)(union gpio_chip_reg *reg, unsigned long data);\n \tbool be_bits;\n+\tbool io_port;\n \tunion gpio_chip_reg reg_dat;\n \tunion gpio_chip_reg reg_set;\n \tunion gpio_chip_reg reg_clr;\n@@ -122,6 +161,8 @@ to_gpio_generic_chip(struct gpio_chip *gc)\n int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n \t\t\t const struct gpio_generic_chip_config *cfg);\n \n+int gpio_generic_chip_port_init(struct gpio_generic_chip *chip,\n+\t\t\t\tconst struct gpio_generic_chip_port_config *cfg);\n /**\n * gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO chip.\n * @chip: Generic GPIO chip to use.\n","prefixes":["RFC","v2","3/3"]}