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Apr 2026 10:24:23.0678\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n d3e3e7f6-bbf3-4fad-f1a2-08de9946d4df","X-MS-Exchange-CrossTenant-Id":"e5e7e96e-8a28-45d6-9093-a40dd5b51a57","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=e5e7e96e-8a28-45d6-9093-a40dd5b51a57;Ip=[162.55.72.218];Helo=[hz-deliver02.de.seppmail.cloud]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tAM4PEPF00025F95.EURPRD83.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem"},"content":"Implement PMIO read and write callbacks for 8-, 16- and 32-bit\nregister accesses using the corresponding port I/O helpers.\n\nSigned-off-by: Jose Javier Rodriguez Barbarin \n---\n drivers/gpio/gpio-mmio.c | 94 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 94 insertions(+)","diff":"diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c\nindex 39326ab7e494..d23c5d275e6b 100644\n--- a/drivers/gpio/gpio-mmio.c\n+++ b/drivers/gpio/gpio-mmio.c\n@@ -124,6 +124,60 @@ static unsigned long gpio_mmio_read32be(union gpio_chip_reg *reg)\n \treturn ioread32be(reg->mmio);\n }\n \n+#ifdef CONFIG_HAS_IOPORT\n+\n+static void gpio_port_write8(union gpio_chip_reg *reg, unsigned long data)\n+{\n+\toutb(data, reg->port);\n+}\n+\n+static unsigned long gpio_port_read8(union gpio_chip_reg *reg)\n+{\n+\treturn inb(reg->port);\n+}\n+\n+static void gpio_port_write16(union gpio_chip_reg *reg, unsigned long data)\n+{\n+\toutw(data, reg->port);\n+}\n+\n+static unsigned long gpio_port_read16(union gpio_chip_reg *reg)\n+{\n+\treturn inw(reg->port);\n+}\n+\n+static void gpio_port_write32(union gpio_chip_reg *reg, unsigned long data)\n+{\n+\toutl(data, reg->port);\n+}\n+\n+static unsigned long gpio_port_read32(union gpio_chip_reg *reg)\n+{\n+\treturn inl(reg->port);\n+}\n+\n+static void gpio_port_write16be(union gpio_chip_reg *reg, unsigned long data)\n+{\n+\toutw(swab16(data), reg->port);\n+}\n+\n+static unsigned long gpio_port_read16be(union gpio_chip_reg *reg)\n+{\n+\treturn swab16(inw(reg->port));\n+}\n+\n+static void gpio_port_write32be(union gpio_chip_reg *reg, unsigned long data)\n+{\n+\toutl(swab32(data), reg->port);\n+}\n+\n+static unsigned long gpio_port_read32be(union gpio_chip_reg *reg)\n+{\n+\treturn swab32(inl(reg->port));\n+}\n+\n+#endif /* CONFIG_HAS_IOPORT */\n+\n static inline bool gpio_chip_reg_is_set(union gpio_chip_reg *reg)\n {\n \treturn reg->port != 0;\n@@ -462,6 +516,46 @@ static int gpio_mmio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,\n \treturn gpio_mmio_dir_return(gc, gpio, true);\n }\n \n+static int gpio_port_setup_accessors(struct device *dev,\n+\t\t\t\t struct gpio_generic_chip *chip,\n+\t\t\t\t bool byte_be)\n+{\n+#ifdef CONFIG_HAS_IOPORT\n+\tswitch (chip->bits) {\n+\tcase 8:\n+\t\tchip->read_reg\t= gpio_port_read8;\n+\t\tchip->write_reg\t= gpio_port_write8;\n+\t\tbreak;\n+\tcase 16:\n+\t\tif (byte_be) {\n+\t\t\tchip->read_reg\t= gpio_port_read16be;\n+\t\t\tchip->write_reg\t= gpio_port_write16be;\n+\t\t} else {\n+\t\t\tchip->read_reg\t= gpio_port_read16;\n+\t\t\tchip->write_reg\t= gpio_port_write16;\n+\t\t}\n+\t\tbreak;\n+\tcase 32:\n+\t\tif (byte_be) {\n+\t\t\tchip->read_reg\t= gpio_port_read32be;\n+\t\t\tchip->write_reg\t= gpio_port_write32be;\n+\t\t} else {\n+\t\t\tchip->read_reg\t= gpio_port_read32;\n+\t\t\tchip->write_reg\t= gpio_port_write32;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(dev, \"unsupported data width %u bits\\n\", chip->bits);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+#else\n+\tdev_err(dev, \"not supported because of missing I/O resource\\n\");\n+\treturn -ENXIO;\n+#endif /* CONFIG_HAS_IOPORT */\n+}\n+\n static int gpio_mmio_setup_accessors(struct device *dev,\n \t\t\t\t struct gpio_generic_chip *chip,\n \t\t\t\t bool byte_be)\n","prefixes":["RFC","v2","2/3"]}