{"id":2222622,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222622/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-9-gaurav.sharma_7@nxp.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413073737.986219-9-gaurav.sharma_7@nxp.com>","date":"2026-04-13T07:37:30","name":"[PATCHv5,08/15] hw/arm/fsl-imx8mm: Add GPIO controllers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4ce980159b3178b9015ab5fd25e0ebae5a18d044","submitter":{"id":92057,"url":"http://patchwork.ozlabs.org/api/1.1/people/92057/?format=json","name":"Gaurav Sharma","email":"gaurav.sharma_7@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-9-gaurav.sharma_7@nxp.com/mbox/","series":[{"id":499658,"url":"http://patchwork.ozlabs.org/api/1.1/series/499658/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499658","date":"2026-04-13T07:37:27","name":"Adding comprehensive support for i.MX8MM EVK board","version":1,"mbox":"http://patchwork.ozlabs.org/series/499658/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222622/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222622/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Mon, 13 Apr 2026 03:37:53 -0400","from inva020.nxp.com (localhost [127.0.0.1])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 633321A158A;\n Mon, 13 Apr 2026 09:37:44 +0200 (CEST)","from aprdc01srsp001v.ap-rdc01.nxp.com\n (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2D81B1A105B;\n Mon, 13 Apr 2026 09:37:44 +0200 (CEST)","from lsv031015.swis.in-blr01.nxp.com\n (lsv031015.swis.in-blr01.nxp.com [10.12.177.77])\n by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 9A9241802227;\n Mon, 13 Apr 2026 15:37:43 +0800 (+08)"],"From":"Gaurav Sharma ","To":"qemu-devel@nongnu.org","Cc":"pbonzini@redhat.com, peter.maydell@linaro.org,\n Gaurav Sharma ,\n Philippe Mathieu-Daude ","Subject":"[PATCHv5 08/15] hw/arm/fsl-imx8mm: Add GPIO controllers","Date":"Mon, 13 Apr 2026 13:07:30 +0530","Message-Id":"<20260413073737.986219-9-gaurav.sharma_7@nxp.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260413073737.986219-1-gaurav.sharma_7@nxp.com>","References":"<20260413073737.986219-1-gaurav.sharma_7@nxp.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Virus-Scanned":"ClamAV using ClamSMTP","Received-SPF":"pass client-ip=92.121.34.13;\n envelope-from=gaurav.sharma_7@nxp.com; helo=inva020.nxp.com","X-Spam_score_int":"-41","X-Spam_score":"-4.2","X-Spam_bar":"----","X-Spam_report":"(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Enabled GPIO controller emulation\nAlso updated the GPIO IRQ lines of iMX8MM\n\nReviewed-by: Philippe Mathieu-Daude \nReviewed-by: Peter Maydell \nSigned-off-by: Gaurav Sharma \n---\n hw/arm/fsl-imx8mm.c | 54 +++++++++++++++++++++++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 14 ++++++++++\n 2 files changed, 68 insertions(+)","diff":"diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex d516e476de..c36baa355f 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -180,6 +180,11 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"gpio%d\", i + 1);\n+ object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);\n+ }\n+\n for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n g_autofree char *name = g_strdup_printf(\"usdhc%d\", i + 1);\n object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);\n@@ -365,6 +370,54 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,\n &s->ocram);\n \n+ /* GPIOs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq_low;\n+ unsigned int irq_high;\n+ } gpio_table[FSL_IMX8MM_NUM_GPIOS] = {\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO1].addr,\n+ FSL_IMX8MM_GPIO1_LOW_IRQ,\n+ FSL_IMX8MM_GPIO1_HIGH_IRQ\n+ },\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO2].addr,\n+ FSL_IMX8MM_GPIO2_LOW_IRQ,\n+ FSL_IMX8MM_GPIO2_HIGH_IRQ\n+ },\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO3].addr,\n+ FSL_IMX8MM_GPIO3_LOW_IRQ,\n+ FSL_IMX8MM_GPIO3_HIGH_IRQ\n+ },\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO4].addr,\n+ FSL_IMX8MM_GPIO4_LOW_IRQ,\n+ FSL_IMX8MM_GPIO4_HIGH_IRQ\n+ },\n+ {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO5].addr,\n+ FSL_IMX8MM_GPIO5_LOW_IRQ,\n+ FSL_IMX8MM_GPIO5_HIGH_IRQ\n+ },\n+ };\n+ object_property_set_bool(OBJECT(&s->gpio[i]), \"has-edge-sel\", true,\n+ &error_abort);\n+ object_property_set_bool(OBJECT(&s->gpio[i]), \"has-upper-pin-irq\",\n+ true, &error_abort);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,\n+ qdev_get_gpio_in(gicdev, gpio_table[i].irq_low));\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,\n+ qdev_get_gpio_in(gicdev, gpio_table[i].irq_high));\n+ }\n+\n /* USDHCs */\n for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {\n static const struct {\n@@ -423,6 +476,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_CCM:\n case FSL_IMX8MM_GIC_DIST:\n case FSL_IMX8MM_GIC_REDIST:\n+ case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:\n case FSL_IMX8MM_PCIE1:\n case FSL_IMX8MM_PCIE_PHY1:\n case FSL_IMX8MM_RAM:\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 3181c02574..4fe27b9575 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -12,6 +12,7 @@\n \n #include \"cpu.h\"\n #include \"hw/char/imx_serial.h\"\n+#include \"hw/gpio/imx_gpio.h\"\n #include \"hw/intc/arm_gicv3_common.h\"\n #include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n@@ -30,6 +31,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)\n \n enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_CPUS = 4,\n+ FSL_IMX8MM_NUM_GPIOS = 5,\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n FSL_IMX8MM_NUM_USDHCS = 3,\n@@ -40,6 +42,7 @@ struct FslImx8mmState {\n \n ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];\n GICv3State gic;\n+ IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS];\n IMX8MPCCMState ccm;\n IMX8MPAnalogState analog;\n IMX7SNVSState snvs;\n@@ -171,6 +174,17 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_UART3_IRQ = 28,\n FSL_IMX8MM_UART4_IRQ = 29,\n \n+ FSL_IMX8MM_GPIO1_LOW_IRQ = 64,\n+ FSL_IMX8MM_GPIO1_HIGH_IRQ = 65,\n+ FSL_IMX8MM_GPIO2_LOW_IRQ = 66,\n+ FSL_IMX8MM_GPIO2_HIGH_IRQ = 67,\n+ FSL_IMX8MM_GPIO3_LOW_IRQ = 68,\n+ FSL_IMX8MM_GPIO3_HIGH_IRQ = 69,\n+ FSL_IMX8MM_GPIO4_LOW_IRQ = 70,\n+ FSL_IMX8MM_GPIO4_HIGH_IRQ = 71,\n+ FSL_IMX8MM_GPIO5_LOW_IRQ = 72,\n+ FSL_IMX8MM_GPIO5_HIGH_IRQ = 73,\n+\n FSL_IMX8MM_PCI_INTA_IRQ = 122,\n FSL_IMX8MM_PCI_INTB_IRQ = 123,\n FSL_IMX8MM_PCI_INTC_IRQ = 124,\n","prefixes":["PATCHv5","08/15"]}