{"id":2222617,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222617/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-15-gaurav.sharma_7@nxp.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413073737.986219-15-gaurav.sharma_7@nxp.com>","date":"2026-04-13T07:37:36","name":"[PATCHv5,14/15] hw/arm/fsl-imx8mm: Adding support for USB controller","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9c2a34db32f04ab13c6921b207cd3c5798987f90","submitter":{"id":92057,"url":"http://patchwork.ozlabs.org/api/1.1/people/92057/?format=json","name":"Gaurav Sharma","email":"gaurav.sharma_7@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-15-gaurav.sharma_7@nxp.com/mbox/","series":[{"id":499658,"url":"http://patchwork.ozlabs.org/api/1.1/series/499658/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499658","date":"2026-04-13T07:37:27","name":"Adding comprehensive support for i.MX8MM EVK board","version":1,"mbox":"http://patchwork.ozlabs.org/series/499658/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222617/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222617/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvK6b6dmCz1yDF\n\tfor ; Mon, 13 Apr 2026 17:39:19 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCBsV-0007Oh-JZ; Mon, 13 Apr 2026 03:38:39 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCBrz-0006xc-Lv\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 03:38:08 -0400","from inva020.nxp.com ([92.121.34.13])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCBrx-0005eL-4h\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 03:38:06 -0400","from inva020.nxp.com (localhost [127.0.0.1])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 934821A3F14;\n Mon, 13 Apr 2026 09:37:46 +0200 (CEST)","from aprdc01srsp001v.ap-rdc01.nxp.com\n (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5AA711A158E;\n Mon, 13 Apr 2026 09:37:46 +0200 (CEST)","from lsv031015.swis.in-blr01.nxp.com\n (lsv031015.swis.in-blr01.nxp.com [10.12.177.77])\n by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id C7E7A1802229;\n Mon, 13 Apr 2026 15:37:45 +0800 (+08)"],"From":"Gaurav Sharma ","To":"qemu-devel@nongnu.org","Cc":"pbonzini@redhat.com, peter.maydell@linaro.org,\n Gaurav Sharma ,\n Philippe Mathieu-Daude ","Subject":"[PATCHv5 14/15] hw/arm/fsl-imx8mm: Adding support for USB controller","Date":"Mon, 13 Apr 2026 13:07:36 +0530","Message-Id":"<20260413073737.986219-15-gaurav.sharma_7@nxp.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260413073737.986219-1-gaurav.sharma_7@nxp.com>","References":"<20260413073737.986219-1-gaurav.sharma_7@nxp.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Virus-Scanned":"ClamAV using ClamSMTP","Received-SPF":"pass client-ip=92.121.34.13;\n envelope-from=gaurav.sharma_7@nxp.com; helo=inva020.nxp.com","X-Spam_score_int":"-41","X-Spam_score":"-4.2","X-Spam_bar":"----","X-Spam_report":"(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"It enables emulation of USB on iMX8MM\nEnables testing and debugging of USB drivers\n\nReviewed-by: Philippe Mathieu-Daude \nReviewed-by: Peter Maydell \nSigned-off-by: Gaurav Sharma \n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 27 +++++++++++++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 6 ++++++\n 3 files changed, 34 insertions(+)","diff":"diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 4095351490..2ed236171a 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -640,6 +640,7 @@ config FSL_IMX8MM\n select SDHCI\n select PCI_EXPRESS_DESIGNWARE\n select PCI_EXPRESS_FSL_IMX8M_PHY\n+ select USB_DWC3\n select WDT_IMX2\n \n config FSL_IMX8MM_EVK\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex a41837a4e8..7f2cc46599 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -202,6 +202,11 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_USBS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"usb%d\", i);\n+ object_initialize_child(obj, name, &s->usb[i], TYPE_USB_DWC3);\n+ }\n+\n for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {\n g_autofree char *name = g_strdup_printf(\"spi%d\", i + 1);\n object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);\n@@ -529,6 +534,27 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n qdev_get_gpio_in(gicdev, usdhc_table[i].irq));\n }\n \n+ /* USBs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_USBS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } usb_table[FSL_IMX8MM_NUM_USBS] = {\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USB1].addr, FSL_IMX8MM_USB1_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_USB2].addr, FSL_IMX8MM_USB2_IRQ },\n+ };\n+\n+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), \"p2\", 1);\n+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), \"p3\", 1);\n+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), \"slots\", 2);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,\n+ qdev_get_gpio_in(gicdev, usb_table[i].irq));\n+ }\n+\n /* ECSPIs */\n for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {\n static const struct {\n@@ -635,6 +661,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_OCRAM:\n case FSL_IMX8MM_SNVS_HP:\n case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:\n+ case FSL_IMX8MM_USB1 ... FSL_IMX8MM_USB2:\n case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3:\n case FSL_IMX8MM_WDOG1 ... FSL_IMX8MM_WDOG3:\n /* device implemented and treated above */\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex c212b6a7a7..cc585bab39 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -25,6 +25,7 @@\n #include \"hw/sd/sdhci.h\"\n #include \"hw/ssi/imx_spi.h\"\n #include \"hw/timer/imx_gpt.h\"\n+#include \"hw/usb/hcd-dwc3.h\"\n #include \"hw/watchdog/wdt_imx2.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n@@ -43,6 +44,7 @@ enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_I2CS = 4,\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n+ FSL_IMX8MM_NUM_USBS = 2,\n FSL_IMX8MM_NUM_USDHCS = 3,\n FSL_IMX8MM_NUM_WDTS = 3,\n };\n@@ -64,6 +66,7 @@ struct FslImx8mmState {\n IMXFECState enet;\n SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];\n+ USBDWC3 usb[FSL_IMX8MM_NUM_USBS];\n DesignwarePCIEHost pcie;\n FslImx8mPciePhyState pcie_phy;\n OrIRQState gpt5_gpt6_irq;\n@@ -202,6 +205,9 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_I2C3_IRQ = 37,\n FSL_IMX8MM_I2C4_IRQ = 38,\n \n+ FSL_IMX8MM_USB1_IRQ = 40,\n+ FSL_IMX8MM_USB2_IRQ = 41,\n+\n FSL_IMX8MM_GPT1_IRQ = 55,\n FSL_IMX8MM_GPT2_IRQ = 54,\n FSL_IMX8MM_GPT3_IRQ = 53,\n","prefixes":["PATCHv5","14/15"]}