{"id":2222608,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222608/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-6-gaurav.sharma_7@nxp.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413073737.986219-6-gaurav.sharma_7@nxp.com>","date":"2026-04-13T07:37:27","name":"[PATCHv5,05/15] hw/arm/fsl-imx8mm: Implemented support for SNVS","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"95e4b63bcb0811d665dd131c4f070e67a0f2acba","submitter":{"id":92057,"url":"http://patchwork.ozlabs.org/api/1.1/people/92057/?format=json","name":"Gaurav Sharma","email":"gaurav.sharma_7@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-6-gaurav.sharma_7@nxp.com/mbox/","series":[{"id":499658,"url":"http://patchwork.ozlabs.org/api/1.1/series/499658/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499658","date":"2026-04-13T07:37:27","name":"Adding comprehensive support for i.MX8MM EVK board","version":1,"mbox":"http://patchwork.ozlabs.org/series/499658/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222608/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222608/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Mon, 13 Apr 2026 03:37:52 -0400","from inva020.nxp.com (localhost [127.0.0.1])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 430591A156B;\n Mon, 13 Apr 2026 09:37:43 +0200 (CEST)","from aprdc01srsp001v.ap-rdc01.nxp.com\n (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 0DFE01A158A;\n Mon, 13 Apr 2026 09:37:43 +0200 (CEST)","from lsv031015.swis.in-blr01.nxp.com\n (lsv031015.swis.in-blr01.nxp.com [10.12.177.77])\n by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 84DB21802228;\n Mon, 13 Apr 2026 15:37:42 +0800 (+08)"],"From":"Gaurav Sharma ","To":"qemu-devel@nongnu.org","Cc":"pbonzini@redhat.com, peter.maydell@linaro.org,\n Gaurav Sharma ","Subject":"[PATCHv5 05/15] hw/arm/fsl-imx8mm: Implemented support for SNVS","Date":"Mon, 13 Apr 2026 13:07:27 +0530","Message-Id":"<20260413073737.986219-6-gaurav.sharma_7@nxp.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260413073737.986219-1-gaurav.sharma_7@nxp.com>","References":"<20260413073737.986219-1-gaurav.sharma_7@nxp.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Virus-Scanned":"ClamAV using ClamSMTP","Received-SPF":"pass client-ip=92.121.34.13;\n envelope-from=gaurav.sharma_7@nxp.com; helo=inva020.nxp.com","X-Spam_score_int":"-41","X-Spam_score":"-4.2","X-Spam_bar":"----","X-Spam_report":"(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"SNVS contains an RTC which allows Linux to deal correctly with time\n\nReviewed-by: Peter Maydell \nSigned-off-by: Gaurav Sharma \n---\n hw/arm/fsl-imx8mm.c | 12 +++++++++++-\n include/hw/arm/fsl-imx8mm.h | 2 ++\n 2 files changed, 13 insertions(+), 1 deletion(-)","diff":"diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex e05e9c9d20..9ca47306c1 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -173,6 +173,8 @@ static void fsl_imx8mm_init(Object *obj)\n \n object_initialize_child(obj, \"analog\", &s->analog, TYPE_IMX8MP_ANALOG);\n \n+ object_initialize_child(obj, \"snvs\", &s->snvs, TYPE_IMX7_SNVS);\n+\n for (i = 0; i < FSL_IMX8MM_NUM_UARTS; i++) {\n g_autofree char *name = g_strdup_printf(\"uart%d\", i + 1);\n object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n@@ -354,7 +356,14 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n memory_region_add_subregion(get_system_memory(),\n fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,\n &s->ocram);\n- \n+\n+ /* SNVS */\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {\n+ return;\n+ }\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr);\n+\n /* Unimplemented devices */\n for (i = 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) {\n switch (i) {\n@@ -364,6 +373,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_GIC_REDIST:\n case FSL_IMX8MM_RAM:\n case FSL_IMX8MM_OCRAM:\n+ case FSL_IMX8MM_SNVS_HP:\n case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:\n /* device implemented and treated above */\n break;\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex df35f0f5ac..8a172b89e0 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -13,6 +13,7 @@\n #include \"cpu.h\"\n #include \"hw/char/imx_serial.h\"\n #include \"hw/intc/arm_gicv3_common.h\"\n+#include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n #include \"hw/misc/imx8mp_ccm.h\"\n #include \"qom/object.h\"\n@@ -37,6 +38,7 @@ struct FslImx8mmState {\n GICv3State gic;\n IMX8MPCCMState ccm;\n IMX8MPAnalogState analog;\n+ IMX7SNVSState snvs;\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n };\n","prefixes":["PATCHv5","05/15"]}