{"id":2222545,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222545/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/patch/20260412174334.3111385-6-wangrui@loongson.cn/","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/1.1/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260412174334.3111385-6-wangrui@loongson.cn>","date":"2026-04-12T17:43:33","name":"[v9,5/6] loongarch: Enable THP-aligned load segments by default on 64-bit","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"63762563629e972f42b6e9895afc7581372fa4ef","submitter":{"id":85150,"url":"http://patchwork.ozlabs.org/api/1.1/people/85150/?format=json","name":"WANG Rui","email":"wangrui@loongson.cn"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/20260412174334.3111385-6-wangrui@loongson.cn/mbox/","series":[{"id":499622,"url":"http://patchwork.ozlabs.org/api/1.1/series/499622/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/list/?series=499622","date":"2026-04-12T17:43:29","name":"elf: THP-aware load segment alignment","version":9,"mbox":"http://patchwork.ozlabs.org/series/499622/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222545/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222545/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=2620:52:6:3111::32; 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server2.sourceware.org","From":"WANG Rui ","To":"libc-alpha@sourceware.org","Cc":"Adhemerval Zanella ,\n Dev Jain , Florian Weimer ,\n Wilco Dijkstra , Xi Ruoyao ,\n WANG Xuerui , caiyinyu ,\n mengqinggang ,\n Huacai Chen , hjl.tools@gmail.com,\n WANG Rui ","Subject":"[PATCH v9 5/6] loongarch: Enable THP-aligned load segments by default\n on 64-bit","Date":"Mon, 13 Apr 2026 01:43:33 +0800","Message-ID":"<20260412174334.3111385-6-wangrui@loongson.cn>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260412174334.3111385-1-wangrui@loongson.cn>","References":"<20260412174334.3111385-1-wangrui@loongson.cn>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"qMiowJBxrsLo2dtpo51rAA--.49052S4","X-CM-SenderInfo":"pzdqw2txl6z05rqj20fqof0/","X-Coremail-Antispam":"1Uk129KBj93XoWxCw1UXw43KF1fGr4rtw1xXrc_yoWrWr1Upr\n WakFs5CF4rWr17C3yak3W7Z3W5WF4rCFs8Cr9xCw4UZryUJr1xZFsFyF1fJFy7J3yxGF4x\n uFnFq3WDuF1rAacCm3ZEXasCq-sJn29KB7ZKAUJUUUU7529EdanIXcx71UUUUU7KY7ZEXa\n sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU\n 0xBIdaVrnRJUUUBYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2\n IYs7xG6rWj6s0DM7CIcVAFz4kK6r1q6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v\n e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI\n 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_\n Gr0_Gr1UM2kKe7AKxVWUXVWUAwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYI\n kI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWrXVW3\n AwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI4\n 8JMxkF7I0En4kS14v26r126r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j\n 6r4UMxCIbckI1I0E14v26r1Y6r17MI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV\n AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2\n 0xvE14v26ryj6F1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4\n v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AK\n xVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8CzutUUUUU==","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org"},"content":"On LoongArch64 Linux, aligning ELF load segments to Transparent Huge Page\n(THP) boundaries provides consistent performance benefits for large\nbinaries by reducing TLB pressure and improving instruction fetch\nefficiency.\n\nEnable THP-based load segment alignment by default on LoongArch64 by\nsetting `glibc.elf.thp=1` during startup. Define the default THP\npage size for load segment alignment on LoongArch64 as 32MB.\n\nThis allows the dynamic loader to apply THP-friendly alignment without\nrequiring the `glibc.elf.thp` tunable to be explicitly set.\n\nBenchmarks\n\nMachine: Loongson 3A6000 (LoongArch64)\nKernel: 6.18.13\n CONFIG_READ_ONLY_THP_FOR_FS=y\n CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y\n\nWorkload 1: building Cargo 1.93.0\nRustc: nightly-2026-02-26\n\n Without patch With patch\ninstructions 3,690,358,948,176 3,690,301,774,568\ncpu-cycles 4,233,025,766,760 4,035,866,635,741\nitlb-misses 9,708,829,532 2,700,014,717\ntime elapsed 302.40 s 289.68 s\n\nInstructions remain essentially unchanged. iTLB misses drop by about\n72%, reducing CPU cycles by about 4.7% and wall time by about 4.2%.\n\nWorkload 2: building Linux kernel v7.0-rc1\nLLVM: 21.1.8\n\n Without patch With patch\ninstructions 14,163,739,876,387 14,169,418,598,675\ncpu-cycles 19,231,890,317,741 16,851,494,928,181\nitlb-misses 91,142,010,440 90,779,245\ntime elapsed 1022.09 s 893.22 s\n\nInstructions remain roughly the same. iTLB misses drop from about 91B\nto about 90M (roughly 99.9% reduction), reducing CPU cycles by about\n12% and wall time by about 12.6%.\n\nReviewed-by: caiyinyu \nSigned-off-by: WANG Rui \n---\n .../unix/sysv/linux/loongarch/cpu-features.c | 6 +++++\n .../loongarch/lp64/dl-map-segment-align.h | 22 +++++++++++++++++++\n 2 files changed, 28 insertions(+)\n create mode 100644 sysdeps/unix/sysv/linux/loongarch/lp64/dl-map-segment-align.h","diff":"diff --git a/sysdeps/unix/sysv/linux/loongarch/cpu-features.c b/sysdeps/unix/sysv/linux/loongarch/cpu-features.c\nindex 0c125e64e2b..7ed54ff53e7 100644\n--- a/sysdeps/unix/sysv/linux/loongarch/cpu-features.c\n+++ b/sysdeps/unix/sysv/linux/loongarch/cpu-features.c\n@@ -27,4 +27,10 @@ init_cpu_features (struct cpu_features *cpu_features)\n GLRO(dl_larch_cpu_features).hwcap = GLRO(dl_hwcap);\n TUNABLE_GET (glibc, cpu, hwcaps, tunable_val_t *,\n \t TUNABLE_CALLBACK (set_hwcaps));\n+\n+#ifdef __LP64__\n+ /* Enable THP-based load segment alignment by default on LoongArch64. */\n+ if (!TUNABLE_IS_INITIALIZED (glibc, elf, thp))\n+ TUNABLE_SET (glibc, elf, thp, 1);\n+#endif\n }\ndiff --git a/sysdeps/unix/sysv/linux/loongarch/lp64/dl-map-segment-align.h b/sysdeps/unix/sysv/linux/loongarch/lp64/dl-map-segment-align.h\nnew file mode 100644\nindex 00000000000..c51ee4ac47e\n--- /dev/null\n+++ b/sysdeps/unix/sysv/linux/loongarch/lp64/dl-map-segment-align.h\n@@ -0,0 +1,22 @@\n+/* _dl_map_segment_align. LoongArch64 Linux version.\n+ Copyright (C) 2026 Free Software Foundation, Inc.\n+ Copyright The GNU Toolchain Authors.\n+ This file is part of the GNU C Library.\n+\n+ The GNU C Library is free software; you can redistribute it and/or\n+ modify it under the terms of the GNU Lesser General Public\n+ License as published by the Free Software Foundation; either\n+ version 2.1 of the License, or (at your option) any later version.\n+\n+ The GNU C Library is distributed in the hope that it will be useful,\n+ but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ Lesser General Public License for more details.\n+\n+ You should have received a copy of the GNU Lesser General Public\n+ License along with the GNU C Library; if not, see\n+ . */\n+\n+#define DL_MAP_DEFAULT_THP_PAGESIZE (32 * 1024 * 1024)\n+\n+#include_next \n","prefixes":["v9","5/6"]}