{"id":2222474,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222474/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/c2838d2c9fc0135bf346ee3754d5e519157bab9d.1775959096.git.chao.liu.zevorn@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"","date":"2026-04-12T02:20:24","name":"[v6,7/7] target/riscv: add sdtrig trigger action=debug mode","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a017f6d188b67c81ae0a3c5ea97f2042803007ef","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/1.1/people/92265/?format=json","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/c2838d2c9fc0135bf346ee3754d5e519157bab9d.1775959096.git.chao.liu.zevorn@gmail.com/mbox/","series":[{"id":499584,"url":"http://patchwork.ozlabs.org/api/1.1/series/499584/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499584","date":"2026-04-12T02:20:20","name":"riscv: add initial sdext support","version":6,"mbox":"http://patchwork.ozlabs.org/series/499584/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222474/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222474/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=CjSdkGAu;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-qv1-xf42.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"RISC-V Debug Specification:\nhttps://github.com/riscv/riscv-debug-spec/releases/tag/1.0\n\nAllow mcontrol/mcontrol6 action=1 when Sdext is enabled. When such a\ntrigger hits, enter Debug Mode with cause=trigger and stop with\nEXCP_DEBUG.\n\nAlso report inst-count triggers in tinfo and read their action field.\n\nSigned-off-by: Chao Liu \nReviewed-by: Daniel Henrique Barboza \nTested-by: Tao Tang \n---\n target/riscv/debug.c | 53 ++++++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 51 insertions(+), 2 deletions(-)","diff":"diff --git a/target/riscv/debug.c b/target/riscv/debug.c\nindex 5877a60c50..6c69c2f796 100644\n--- a/target/riscv/debug.c\n+++ b/target/riscv/debug.c\n@@ -110,6 +110,8 @@ static trigger_action_t get_trigger_action(CPURISCVState *env,\n action = (tdata1 & TYPE6_ACTION) >> 12;\n break;\n case TRIGGER_TYPE_INST_CNT:\n+ action = tdata1 & ITRIGGER_ACTION;\n+ break;\n case TRIGGER_TYPE_INT:\n case TRIGGER_TYPE_EXCP:\n case TRIGGER_TYPE_EXT_SRC:\n@@ -280,6 +282,7 @@ static target_ulong textra_validate(CPURISCVState *env, target_ulong tdata3)\n \n static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)\n {\n+ CPUState *cs = env_cpu(env);\n trigger_action_t action = get_trigger_action(env, trigger_index);\n \n switch (action) {\n@@ -289,6 +292,21 @@ static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)\n riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);\n break;\n case DBG_ACTION_DBG_MODE:\n+ if (!env_archcpu(env)->cfg.ext_sdext) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"trigger action=debug mode requires Sdext\\n\");\n+ riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);\n+ }\n+ riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_TRIGGER);\n+ /*\n+ * If this came from the Trigger Module's CPU breakpoint/watchpoint,\n+ * we're already returning via EXCP_DEBUG. Otherwise, stop now.\n+ */\n+ if (cs->exception_index != EXCP_DEBUG) {\n+ cs->exception_index = EXCP_DEBUG;\n+ cpu_loop_exit_restore(cs, GETPC());\n+ }\n+ break;\n case DBG_ACTION_TRACE0:\n case DBG_ACTION_TRACE1:\n case DBG_ACTION_TRACE2:\n@@ -441,6 +459,7 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,\n {\n target_ulong val;\n uint32_t size;\n+ uint32_t action;\n \n /* validate the generic part first */\n val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH);\n@@ -448,11 +467,25 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,\n /* validate unimplemented (always zero) bits */\n warn_always_zero_bit(ctrl, TYPE2_MATCH, \"match\");\n warn_always_zero_bit(ctrl, TYPE2_CHAIN, \"chain\");\n- warn_always_zero_bit(ctrl, TYPE2_ACTION, \"action\");\n warn_always_zero_bit(ctrl, TYPE2_TIMING, \"timing\");\n warn_always_zero_bit(ctrl, TYPE2_SELECT, \"select\");\n warn_always_zero_bit(ctrl, TYPE2_HIT, \"hit\");\n \n+ action = (ctrl & TYPE2_ACTION) >> 12;\n+ if (action == DBG_ACTION_BP) {\n+ val |= ctrl & TYPE2_ACTION;\n+ } else if (action == DBG_ACTION_DBG_MODE) {\n+ if (env_archcpu(env)->cfg.ext_sdext) {\n+ val |= ctrl & TYPE2_ACTION;\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"trigger action=debug mode requires Sdext\\n\");\n+ }\n+ } else {\n+ qemu_log_mask(LOG_UNIMP, \"trigger action: %u is not supported\\n\",\n+ action);\n+ }\n+\n /* validate size encoding */\n size = type2_breakpoint_size(env, ctrl);\n if (access_size[size] == -1) {\n@@ -569,6 +602,7 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,\n {\n target_ulong val;\n uint32_t size;\n+ uint32_t action;\n \n /* validate the generic part first */\n val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6);\n@@ -576,11 +610,25 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,\n /* validate unimplemented (always zero) bits */\n warn_always_zero_bit(ctrl, TYPE6_MATCH, \"match\");\n warn_always_zero_bit(ctrl, TYPE6_CHAIN, \"chain\");\n- warn_always_zero_bit(ctrl, TYPE6_ACTION, \"action\");\n warn_always_zero_bit(ctrl, TYPE6_TIMING, \"timing\");\n warn_always_zero_bit(ctrl, TYPE6_SELECT, \"select\");\n warn_always_zero_bit(ctrl, TYPE6_HIT, \"hit\");\n \n+ action = (ctrl & TYPE6_ACTION) >> 12;\n+ if (action == DBG_ACTION_BP) {\n+ val |= ctrl & TYPE6_ACTION;\n+ } else if (action == DBG_ACTION_DBG_MODE) {\n+ if (env_archcpu(env)->cfg.ext_sdext) {\n+ val |= ctrl & TYPE6_ACTION;\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"trigger action=debug mode requires Sdext\\n\");\n+ }\n+ } else {\n+ qemu_log_mask(LOG_UNIMP, \"trigger action: %u is not supported\\n\",\n+ action);\n+ }\n+\n /* validate size encoding */\n size = extract32(ctrl, 16, 4);\n if (access_size[size] == -1) {\n@@ -919,6 +967,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env)\n {\n /* assume all triggers support the same types of triggers */\n return BIT(TRIGGER_TYPE_AD_MATCH) |\n+ BIT(TRIGGER_TYPE_INST_CNT) |\n BIT(TRIGGER_TYPE_AD_MATCH6);\n }\n \n","prefixes":["v6","7/7"]}