{"id":2222287,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222287/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260411070637.72421-3-james.hilliard1@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260411070637.72421-3-james.hilliard1@gmail.com>","date":"2026-04-11T07:06:29","name":"[3/9] target/mips: add Octeon LA* atomic instructions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0c77ff9c7d86e96edf89deb9b04fe25e46be23c3","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.1/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260411070637.72421-3-james.hilliard1@gmail.com/mbox/","series":[{"id":499531,"url":"http://patchwork.ozlabs.org/api/1.1/series/499531/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499531","date":"2026-04-11T07:06:33","name":"[1/9] linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accesses","version":1,"mbox":"http://patchwork.ozlabs.org/series/499531/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222287/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222287/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=LbKVGRp5;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4ft4X26Wkmz1yGb\n\tfor ; Sat, 11 Apr 2026 17:08:34 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wBSQr-0001Zw-A0; Sat, 11 Apr 2026 03:07:05 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wBSQp-0001ZQ-4S\n for qemu-devel@nongnu.org; Sat, 11 Apr 2026 03:07:03 -0400","from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wBSQn-0000zm-AK\n for qemu-devel@nongnu.org; Sat, 11 Apr 2026 03:07:02 -0400","by mail-oa1-x2a.google.com with SMTP id\n 586e51a60fabf-415c8a4d2e6so1350584fac.0\n for ; Sat, 11 Apr 2026 00:07:00 -0700 (PDT)","from Mac.localdomain (71-218-253-186.hlrn.qwest.net.\n [71.218.253.186]) by smtp.gmail.com with ESMTPSA id\n 5614622812f47-478a0f1e841sm2651091b6e.5.2026.04.11.00.06.57\n (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256);\n Sat, 11 Apr 2026 00:06:58 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1775891218; x=1776496018; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=JnbBviPfCRVExB4FeTwpdafOvkA6EOmi1jkVfNSRtXs=;\n b=LbKVGRp5c1VgPBqcydGISHTmu+HA0LtJBVtjU7O56TxTfZdonGZNQy/Ac4rA4cn7Tz\n aYtG2uYxe5PeTlXBHlv1edafiRGqM+pSb4ZPHQfyy89exZx1WA/xFZ7xGHCiDGPoNR7p\n 1umTV+JSs6scRcOlXKejDFeE5jMxu8pr2t82RawBzMiSPzGnXoqQ964fGxNktl5k3JAF\n V9tinzVb4L8TMRCnVNG9I5a9WFASPal/7QphB14DGh7x0fm7Fw2fV0xHqwljnAi9Zogb\n uHftBJZnuq85yENnVC39XauGWNHRbS5upNx4O5aDaWj7jd2aG9owBJXOw26xaV2OsNS3\n BKHw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775891218; x=1776496018;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=JnbBviPfCRVExB4FeTwpdafOvkA6EOmi1jkVfNSRtXs=;\n b=owolZRoZt5071OA96npvhSSqWiH4GB1UA8+p4wCCQAImgXc5FkHIG+S4S2ky7qb+AL\n PshgUuGkJd4osm+kc0HJBXaYkKjm2O22yEkJ5DR7QvFhr3ziSiEWIIrgaoBnRgx/yCs4\n 6dFFmgFfyZx8hjJ4zbrIWWi3D3R5Bg4jW0LINEgpbiF1CHST+tIdTwkFJN4m6vcmDXTE\n asbkdD1haHcAecBHDE4N9ndjAZJ5/YXBjYPnGBzkYFDXe5A2ZKuLq79yutYJWK7jkfct\n RbzJZQPw3agQVFRwZOO0tYGIdE3nqGP52IMlb0Hohl0WBKlIpVvY0RWYUer5V3qCTRd+\n IEfQ==","X-Gm-Message-State":"AOJu0YwDWCJxIktgzUb5B9ohnVbYnuk4408oWNg48vwMDJ2fCHhLTAWy\n IDFjazW8/WEbk7Fp97vZivT8Zv6DtzRCthp4YDEL11Vj3982QrHJuUWYCdIWtcUX/Wc=","X-Gm-Gg":"AeBDieteyogI8fIQgcLFX1ql2GP3kZGP2htXhvY2vBFdVHxxzucBTCQxM1wgyk9GJFU\n U7gUnQXytW06Mq+VqRPiiqIIslARnMTslDbSsZj8MOpx6w7RbMQ9GpYNdwDtajVcO+LljLpVdsB\n 4gM3yE6fVNtj8YYf3RFFSjngIBVNWM8dpuS9Skf2NBhKGcbvZ3wp+LpHeFQrgPBSgYDEXrXB1QB\n B77dhIQrGmwd6lVxkn1B/CfrJTudNf9DWQrQ8PLuhCcBZhZ7qnRI4LMg2XHcKTbqiRFIOyOBl7B\n E9rI+47u33ARBiePaK25fZOBQMlyM3gsKnv293p6GTxhMQ14bxW5P1JV6G3ifx/N43FcUJqnF5r\n yMaBAf1LQ3iFqF1yYUhjkyYikXro+jImkLqQ8kuACvxTcF87gZzJR99bjfpYq1k+vQo3NvwOPpZ\n 8RVHO/DCJo8LXgM0QIs5amL2EqEIX0Y3E2Gq1LDB/a0pEMonMuNPcVy3QLLybUgR81jEWWdkPlC\n TMsseivNJn14W8X2DTRJyRWcO3oRbW1nIdygb+FHs9Kk2pSftP+aYQ+5jJ4iNaPGn/cRhA=","X-Received":"by 2002:a05:6808:2202:b0:450:4782:2b0e with SMTP id\n 5614622812f47-4789d03fd6bmr2947587b6e.15.1775891218559;\n Sat, 11 Apr 2026 00:06:58 -0700 (PDT)","From":"James Hilliard ","To":"qemu-devel@nongnu.org","Cc":"James Hilliard ,\n Laurent Vivier ,\n Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-?=\n\t=?utf-8?q?Daud=C3=A9?= ,\n Aurelien Jarno , Jiaxun Yang ,\n Aleksandar Rikalo , Huacai Chen ","Subject":"[PATCH 3/9] target/mips: add Octeon LA* atomic instructions","Date":"Sat, 11 Apr 2026 01:06:29 -0600","Message-ID":"<20260411070637.72421-3-james.hilliard1@gmail.com>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260411070637.72421-1-james.hilliard1@gmail.com>","References":"<20260411070637.72421-1-james.hilliard1@gmail.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2001:4860:4864:20::2a;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x2a.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Implement the Octeon LA* read-modify-write atomic instruction family:\nLAI/LAID, LAD/LADD, LAA/LAAD, LAS/LASD, LAC/LACD, and LAW/LAWD.\n\nThese operations are architecturally distinct from SAA/SAAD and are\nused by existing Octeon user-mode code for atomic counters, bit\noperations, and exchange-style updates.\n\nSigned-off-by: James Hilliard \n---\n target/mips/tcg/octeon.decode | 17 +++\n target/mips/tcg/octeon_translate.c | 170 +++++++++++++++++++++++++++++\n 2 files changed, 187 insertions(+)","diff":"diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex d90a194b54..0f5fe83609 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -59,6 +59,23 @@ V3MULU 011100 ..... ..... ..... 00000 010001 @r3\n SAA 011100 ..... ..... 00000 00000 011000 @saa\n SAAD 011100 ..... ..... 00000 00000 011001 @saa\n \n+&la base rd\n+&laa base add rd\n+@la ...... base:5 ..... rd:5 ........... &la\n+@laa ...... base:5 add:5 rd:5 ........... &laa\n+LAI 011100 ..... 00000 ..... 00010 011111 @la\n+LAID 011100 ..... 00000 ..... 00011 011111 @la\n+LAD 011100 ..... 00000 ..... 00110 011111 @la\n+LADD 011100 ..... 00000 ..... 00111 011111 @la\n+LAA 011100 ..... ..... ..... 10010 011111 @laa\n+LAAD 011100 ..... ..... ..... 10011 011111 @laa\n+LAS 011100 ..... 00000 ..... 01010 011111 @la\n+LASD 011100 ..... 00000 ..... 01011 011111 @la\n+LAC 011100 ..... 00000 ..... 01110 011111 @la\n+LACD 011100 ..... 00000 ..... 01111 011111 @la\n+LAW 011100 ..... ..... ..... 10110 011111 @laa\n+LAWD 011100 ..... ..... ..... 10111 011111 @laa\n+\n &zcb base\n ZCB 011100 base:5 00000 00000 11100 011111 &zcb\n \ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex 67b8634dff..9ac20196de 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -232,6 +232,164 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)\n return true;\n }\n \n+static bool trans_la_common(DisasContext *ctx, int base, int add, int rd,\n+ int64_t imm, bool dw)\n+{\n+ TCGv addr = tcg_temp_new();\n+\n+ gen_base_offset_addr(ctx, addr, base, 0);\n+\n+ if (dw) {\n+ check_mips_64(ctx);\n+ if (ctx->base.is_jmp != DISAS_NEXT) {\n+ return true;\n+ }\n+#if TARGET_LONG_BITS == 64\n+ TCGv value = tcg_temp_new();\n+ TCGv old = tcg_temp_new();\n+ MemOp amo = mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask;\n+\n+ if (add >= 0) {\n+ gen_load_gpr(value, add);\n+ } else {\n+ tcg_gen_movi_tl(value, imm);\n+ }\n+\n+ tcg_gen_atomic_fetch_add_tl(old, addr, value, ctx->mem_idx, amo);\n+ gen_store_gpr(old, rd);\n+#endif\n+ } else {\n+ TCGv old = tcg_temp_new();\n+ TCGv_i32 value32 = tcg_temp_new_i32();\n+ TCGv_i32 old32 = tcg_temp_new_i32();\n+ MemOp amo = mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask;\n+\n+ if (add < 0) {\n+ tcg_gen_movi_i32(value32, imm);\n+ } else {\n+ TCGv value = tcg_temp_new();\n+\n+ gen_load_gpr(value, add);\n+ tcg_gen_trunc_tl_i32(value32, value);\n+ }\n+\n+ tcg_gen_atomic_fetch_add_i32(old32, addr, value32, ctx->mem_idx, amo);\n+ tcg_gen_ext_i32_tl(old, old32);\n+ gen_store_gpr(old, rd);\n+ }\n+\n+ return true;\n+}\n+\n+static bool trans_law_common(DisasContext *ctx, int base, int add, int rd,\n+ int64_t imm, bool dw)\n+{\n+ TCGv addr = tcg_temp_new();\n+\n+ gen_base_offset_addr(ctx, addr, base, 0);\n+\n+ if (dw) {\n+ check_mips_64(ctx);\n+ if (ctx->base.is_jmp != DISAS_NEXT) {\n+ return true;\n+ }\n+#if TARGET_LONG_BITS == 64\n+ TCGv value = tcg_temp_new();\n+ TCGv old = tcg_temp_new();\n+ MemOp amo = mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask;\n+\n+ if (add >= 0) {\n+ gen_load_gpr(value, add);\n+ } else {\n+ tcg_gen_movi_tl(value, imm);\n+ }\n+\n+ tcg_gen_atomic_xchg_tl(old, addr, value, ctx->mem_idx, amo);\n+ gen_store_gpr(old, rd);\n+#endif\n+ } else {\n+ TCGv old = tcg_temp_new();\n+ TCGv_i32 value32 = tcg_temp_new_i32();\n+ TCGv_i32 old32 = tcg_temp_new_i32();\n+ MemOp amo = mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask;\n+\n+ if (add >= 0) {\n+ TCGv value = tcg_temp_new();\n+\n+ gen_load_gpr(value, add);\n+ tcg_gen_trunc_tl_i32(value32, value);\n+ } else {\n+ tcg_gen_movi_i32(value32, imm);\n+ }\n+\n+ tcg_gen_atomic_xchg_i32(old32, addr, value32, ctx->mem_idx, amo);\n+ tcg_gen_ext_i32_tl(old, old32);\n+ gen_store_gpr(old, rd);\n+ }\n+\n+ return true;\n+}\n+\n+static bool trans_lai(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, -1, a->rd, 1, false);\n+}\n+\n+static bool trans_laid(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, -1, a->rd, 1, true);\n+}\n+\n+static bool trans_lad(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, -1, a->rd, -1, false);\n+}\n+\n+static bool trans_ladd(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, -1, a->rd, -1, true);\n+}\n+\n+static bool trans_laa(DisasContext *ctx, arg_laa *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, a->add, a->rd, 0, false);\n+}\n+\n+static bool trans_laad(DisasContext *ctx, arg_laa *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, a->add, a->rd, 0, true);\n+}\n+\n+static bool trans_las(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, -1, a->rd, -1, false);\n+}\n+\n+static bool trans_lasd(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, -1, a->rd, -1, true);\n+}\n+\n+static bool trans_lac(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, -1, a->rd, 0, false);\n+}\n+\n+static bool trans_lacd(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, -1, a->rd, 0, true);\n+}\n+\n+static bool trans_law(DisasContext *ctx, arg_laa *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, a->add, a->rd, 0, false);\n+}\n+\n+static bool trans_lawd(DisasContext *ctx, arg_laa *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, a->add, a->rd, 0, true);\n+}\n+\n static bool trans_ZCB(DisasContext *ctx, arg_zcb *a)\n {\n TCGv addr = tcg_temp_new();\n@@ -314,6 +472,18 @@ static bool trans_vmul(DisasContext *ctx, arg_decode_ext_octeon1 *a,\n \n TRANS(SAA, trans_saa, MO_UL);\n TRANS(SAAD, trans_saa, MO_UQ);\n+TRANS(LAI, trans_lai, 0);\n+TRANS(LAID, trans_laid, 0);\n+TRANS(LAD, trans_lad, 0);\n+TRANS(LADD, trans_ladd, 0);\n+TRANS(LAA, trans_laa, 0);\n+TRANS(LAAD, trans_laad, 0);\n+TRANS(LAS, trans_las, 0);\n+TRANS(LASD, trans_lasd, 0);\n+TRANS(LAC, trans_lac, 0);\n+TRANS(LACD, trans_lacd, 0);\n+TRANS(LAW, trans_law, 0);\n+TRANS(LAWD, trans_lawd, 0);\n TRANS(LBX, trans_lx, MO_SB);\n TRANS(LBUX, trans_lx, MO_UB);\n TRANS(LHX, trans_lx, MO_SW);\n","prefixes":["3/9"]}