{"id":2222059,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222059/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/6b473acaf5fc50ddbe89d795edc2b0eb9da63be9.1775843299.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<6b473acaf5fc50ddbe89d795edc2b0eb9da63be9.1775843299.git.matheus.bernardino@oss.qualcomm.com>","date":"2026-04-10T17:56:03","name":"[v4,15/16] tests/hexagon: add tests for v68 HVX IEEE float comparisons","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2cdf38ba30ef785f3c9df886fee03be985b2c9da","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/1.1/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/6b473acaf5fc50ddbe89d795edc2b0eb9da63be9.1775843299.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":499491,"url":"http://patchwork.ozlabs.org/api/1.1/series/499491/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499491","date":"2026-04-10T17:55:50","name":"hexagon: add missing HVX float instructions","version":4,"mbox":"http://patchwork.ozlabs.org/series/499491/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222059/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222059/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com 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DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Reviewed-by: Taylor Simpson \nSigned-off-by: Matheus Tavares Bernardino \n---\n tests/tcg/hexagon/hex_test.h | 1 +\n tests/tcg/hexagon/fp_hvx_cmp.c | 224 ++++++++++++++++++++++++++++++\n tests/tcg/hexagon/Makefile.target | 3 +\n 3 files changed, 228 insertions(+)\n create mode 100644 tests/tcg/hexagon/fp_hvx_cmp.c","diff":"diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h\nindex d5da8ad240..79d30ec61c 100644\n--- a/tests/tcg/hexagon/hex_test.h\n+++ b/tests/tcg/hexagon/hex_test.h\n@@ -115,6 +115,7 @@ const uint16_t HF_INF = 0x7c00;\n const uint16_t HF_INF_neg = 0xfc00;\n const uint16_t HF_QNaN = 0x7e00;\n const uint16_t HF_SNaN = 0x7d00;\n+const uint16_t HF_SNaN_neg = 0xfd00;\n const uint16_t HF_QNaN_neg = 0xfe00;\n const uint16_t HF_zero = 0x0000;\n const uint16_t HF_zero_neg = 0x8000;\ndiff --git a/tests/tcg/hexagon/fp_hvx_cmp.c b/tests/tcg/hexagon/fp_hvx_cmp.c\nnew file mode 100644\nindex 0000000000..b1352c786a\n--- /dev/null\n+++ b/tests/tcg/hexagon/fp_hvx_cmp.c\n@@ -0,0 +1,224 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#if __HEXAGON_ARCH__ > 75\n+#error \"After v75, compiler will replace some FP HVX instructions.\"\n+#endif\n+\n+int err;\n+#include \"hvx_misc.h\"\n+#include \"hex_test.h\"\n+\n+#define MAX_TESTS_hf (MAX_VEC_SIZE_BYTES / 2)\n+#define MAX_TESTS_sf (MAX_VEC_SIZE_BYTES / 4)\n+\n+#define TRUE_MASK_sf 0xffffffff\n+#define TRUE_MASK_hf 0xffff\n+\n+static const char *comparisons[MAX_TESTS_sf][2];\n+static HVX_Vector *hvx_output = (HVX_Vector *)&output[0];\n+static HVX_Vector buffers[2], true_vec, false_vec;\n+static int exp_index;\n+\n+#define ADD_TEST_CMP(TYPE, VAL1, VAL2, EXP) do { \\\n+ ((MMVector *)&buffers[0])->TYPE[exp_index] = VAL1; \\\n+ ((MMVector *)&buffers[1])->TYPE[exp_index] = VAL2; \\\n+ expect[0].TYPE[exp_index] = EXP ? TRUE_MASK_##TYPE : 0; \\\n+ comparisons[exp_index][0] = #VAL1; \\\n+ comparisons[exp_index][1] = #VAL2; \\\n+ assert(exp_index < MAX_TESTS_##TYPE); \\\n+ exp_index++; \\\n+} while (0)\n+\n+#define TEST_CMP_GT(TYPE, VAL1, VAL2) do { \\\n+ ADD_TEST_CMP(TYPE, VAL1, VAL2, true); \\\n+ ADD_TEST_CMP(TYPE, VAL2, VAL1, false); \\\n+} while (0)\n+\n+#define PREP_TEST() do { \\\n+ memset(&buffers, 0, sizeof(buffers)); \\\n+ memset(expect, 0, sizeof(expect)); \\\n+ exp_index = 0; \\\n+} while (0)\n+\n+#define CHECK(TYPE, TYPESZ) do { \\\n+ HVX_VectorPred pred = Q6_Q_vcmp_gt_V##TYPE##V##TYPE(buffers[0], buffers[1]); \\\n+ *hvx_output = Q6_V_vmux_QVV(pred, true_vec, false_vec); \\\n+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / TYPESZ; j++) { \\\n+ if (output[0].TYPE[j] != expect[0].TYPE[j]) { \\\n+ printf(\"ERROR: expected %s %s %s\\n\", comparisons[j][0], \\\n+ (expect[0].TYPE[j] != 0 ? \">\" : \"<=\"), comparisons[j][1]); \\\n+ err++; \\\n+ } \\\n+ } \\\n+} while (0)\n+\n+static void test_cmp_sf(void)\n+{\n+ /*\n+ * General ordering for sf:\n+ * QNaN > SNaN > +Inf > numbers > -Inf > SNaN_neg > QNaN_neg\n+ */\n+\n+ /* Test equality */\n+ PREP_TEST();\n+ ADD_TEST_CMP(sf, raw_sf(2.2), raw_sf(2.2), false);\n+ ADD_TEST_CMP(sf, SF_SNaN, SF_SNaN, false);\n+ CHECK(sf, 4);\n+\n+ /* Common numbers */\n+ PREP_TEST();\n+ TEST_CMP_GT(sf, raw_sf(2.2), raw_sf(2.1));\n+ TEST_CMP_GT(sf, raw_sf(0), raw_sf(-2.2));\n+ CHECK(sf, 4);\n+\n+ /* Infinity vs Infinity/NaN */\n+ PREP_TEST();\n+ TEST_CMP_GT(sf, SF_QNaN, SF_INF);\n+ TEST_CMP_GT(sf, SF_SNaN, SF_INF);\n+ TEST_CMP_GT(sf, SF_INF, SF_INF_neg);\n+ TEST_CMP_GT(sf, SF_INF, SF_SNaN_neg);\n+ TEST_CMP_GT(sf, SF_INF, SF_QNaN_neg);\n+ TEST_CMP_GT(sf, SF_INF_neg, SF_SNaN_neg);\n+ TEST_CMP_GT(sf, SF_INF_neg, SF_QNaN_neg);\n+ TEST_CMP_GT(sf, SF_SNaN, SF_INF_neg);\n+ TEST_CMP_GT(sf, SF_QNaN, SF_INF_neg);\n+ CHECK(sf, 4);\n+\n+ /* NaN vs NaN */\n+ PREP_TEST();\n+ TEST_CMP_GT(sf, SF_QNaN, SF_SNaN);\n+ TEST_CMP_GT(sf, SF_SNaN, SF_SNaN_neg);\n+ TEST_CMP_GT(sf, SF_SNaN_neg, SF_QNaN_neg);\n+ CHECK(sf, 4);\n+\n+ /* NaN vs non-NaN */\n+ PREP_TEST();\n+ TEST_CMP_GT(sf, SF_QNaN, SF_one);\n+ TEST_CMP_GT(sf, SF_SNaN, SF_one);\n+ TEST_CMP_GT(sf, SF_one, SF_QNaN_neg);\n+ TEST_CMP_GT(sf, SF_one, SF_SNaN_neg);\n+ CHECK(sf, 4);\n+}\n+\n+static void test_cmp_hf(void)\n+{\n+ /*\n+ * General ordering for hf:\n+ * QNaN > SNaN > +Inf > numbers > -Inf > QSNaN_neg > QNaN_neg\n+ */\n+\n+ /* Test equality */\n+ PREP_TEST();\n+ ADD_TEST_CMP(hf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.2), false);\n+ ADD_TEST_CMP(hf, HF_SNaN, HF_SNaN, false);\n+ CHECK(hf, 2);\n+\n+ /* Common numbers */\n+ PREP_TEST();\n+ TEST_CMP_GT(hf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.1));\n+ TEST_CMP_GT(hf, raw_hf((_Float16)0), raw_hf((_Float16)-2.2));\n+ CHECK(hf, 2);\n+\n+ /* Infinity vs Infinity/NaN */\n+ PREP_TEST();\n+ TEST_CMP_GT(hf, HF_QNaN, HF_INF);\n+ TEST_CMP_GT(hf, HF_SNaN, HF_INF);\n+ TEST_CMP_GT(hf, HF_INF, HF_INF_neg);\n+ TEST_CMP_GT(hf, HF_INF, HF_SNaN_neg);\n+ TEST_CMP_GT(hf, HF_INF, HF_QNaN_neg);\n+ TEST_CMP_GT(hf, HF_INF_neg, HF_SNaN_neg);\n+ TEST_CMP_GT(hf, HF_INF_neg, HF_QNaN_neg);\n+ TEST_CMP_GT(hf, HF_SNaN, HF_INF_neg);\n+ TEST_CMP_GT(hf, HF_QNaN, HF_INF_neg);\n+ CHECK(hf, 2);\n+\n+ /* NaN vs NaN */\n+ PREP_TEST();\n+ TEST_CMP_GT(hf, HF_QNaN, HF_SNaN);\n+ TEST_CMP_GT(hf, HF_SNaN, HF_SNaN_neg);\n+ TEST_CMP_GT(hf, HF_SNaN_neg, HF_QNaN_neg);\n+ CHECK(hf, 2);\n+\n+ /* NaN vs non-NaN */\n+ PREP_TEST();\n+ TEST_CMP_GT(hf, HF_QNaN, HF_one);\n+ TEST_CMP_GT(hf, HF_SNaN, HF_one);\n+ TEST_CMP_GT(hf, HF_one, HF_QNaN_neg);\n+ TEST_CMP_GT(hf, HF_one, HF_SNaN_neg);\n+ CHECK(hf, 2);\n+}\n+\n+static void check_byte_pred(HVX_VectorPred pred, int byte_idx, uint8_t exp_mask,\n+ int line)\n+{\n+ /*\n+ * Note: ((uint8_t *)&pred)[N] returns the expanded value of bit N:\n+ * 0xFF if bit is set, 0x00 if clear.\n+ */\n+ for (int i = 0; i < 8; i++) {\n+ int idx = byte_idx * 8 + i;\n+ int val = ((uint8_t *)&pred)[idx];\n+ int exp = (exp_mask >> i) & 1 ? 0xff : 0x00;\n+ if (exp != val) {\n+ printf(\"ERROR line %d: pred bit %d is 0x%x, should be 0x%x\\n\",\n+ line, idx, val, exp);\n+ err++;\n+ }\n+ }\n+}\n+\n+#define CHECK_BYTE_PRED(PRED, BYTE, EXP) check_byte_pred(PRED, BYTE, EXP, __LINE__)\n+\n+static void test_cmp_variants(void)\n+{\n+ HVX_VectorPred pred;\n+\n+ /*\n+ * Setup: comparison result will have bits 4-7 set (0xF0 in pred byte 0)\n+ * - sf[0]: SF_zero > SF_one = false -> bits 0-3 = 0\n+ * - sf[1]: SF_one > SF_zero = true -> bits 4-7 = 1\n+ */\n+ PREP_TEST();\n+ ADD_TEST_CMP(sf, SF_zero, SF_one, false);\n+ ADD_TEST_CMP(sf, SF_one, SF_zero, true);\n+\n+ /* greater and: 0xF0 & 0xF0 = 0xF0 */\n+ memset(&pred, 0xF0, sizeof(pred));\n+ pred = Q6_Q_vcmp_gtand_QVsfVsf(pred, buffers[0], buffers[1]);\n+ CHECK_BYTE_PRED(pred, 0, 0xF0);\n+\n+ /* greater or: 0x0F | 0xF0 = 0xFF */\n+ memset(&pred, 0x0F, sizeof(pred));\n+ pred = Q6_Q_vcmp_gtor_QVsfVsf(pred, buffers[0], buffers[1]);\n+ CHECK_BYTE_PRED(pred, 0, 0xFF);\n+\n+ /* greater xor: 0xFF ^ 0xF0 = 0x0F */\n+ memset(&pred, 0xFF, sizeof(pred));\n+ pred = Q6_Q_vcmp_gtxacc_QVsfVsf(pred, buffers[0], buffers[1]);\n+ CHECK_BYTE_PRED(pred, 0, 0x0F);\n+}\n+\n+int main(void)\n+{\n+ memset(&true_vec, 0xff, sizeof(true_vec));\n+ memset(&false_vec, 0, sizeof(false_vec));\n+\n+ test_cmp_sf();\n+ test_cmp_hf();\n+ test_cmp_variants();\n+\n+ puts(err ? \"FAIL\" : \"PASS\");\n+ return err ? 1 : 0;\n+}\ndiff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target\nindex 1abc5f2124..92bdedf661 100644\n--- a/tests/tcg/hexagon/Makefile.target\n+++ b/tests/tcg/hexagon/Makefile.target\n@@ -52,6 +52,7 @@ HEX_TESTS += hvx_misc\n HEX_TESTS += hvx_histogram\n HEX_TESTS += fp_hvx\n HEX_TESTS += fp_hvx_cvt\n+HEX_TESTS += fp_hvx_cmp\n HEX_TESTS += fp_hvx_disabled\n HEX_TESTS += invalid-slots\n HEX_TESTS += invalid-encoding\n@@ -135,6 +136,8 @@ fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h hex_test.h\n fp_hvx_disabled: CFLAGS += -mhvx -mhvx-ieee-fp\n fp_hvx_cvt: fp_hvx_cvt.c hvx_misc.h hex_test.h\n fp_hvx_cvt: CFLAGS += -mhvx -mhvx-ieee-fp\n+fp_hvx_cmp: fp_hvx_cmp.c hvx_misc.h hex_test.h\n+fp_hvx_cmp: CFLAGS += -mhvx -mhvx-ieee-fp\n \n run-fp_hvx_disabled: QEMU_OPTS += -cpu v73,ieee-fp=false\n \n","prefixes":["v4","15/16"]}