{"id":2222055,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222055/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/ac72a36fd8483a7b30e09a99026a557c5bb80b02.1775843299.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"","date":"2026-04-10T17:55:52","name":"[v4,04/16] hexagon: group cpu configurations in their own struct","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"26ea5c655d2a38ecce9ddea56cc0a310ee537ac3","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/1.1/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/ac72a36fd8483a7b30e09a99026a557c5bb80b02.1775843299.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":499491,"url":"http://patchwork.ozlabs.org/api/1.1/series/499491/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499491","date":"2026-04-10T17:55:50","name":"hexagon: add missing HVX float instructions","version":4,"mbox":"http://patchwork.ozlabs.org/series/499491/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222055/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222055/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=hsB2mEdk;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=VGR/dt1G;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsl066pVZz1y2d\n\tfor ; Sat, 11 Apr 2026 03:58:14 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wBG5b-0006oO-Py; Fri, 10 Apr 2026 13:56:19 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wBG5Y-0006mX-I5\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:16 -0400","from mx0b-0031df01.pphosted.com ([205.220.180.131])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wBG5V-0001YG-LM\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:16 -0400","from pps.filterd (m0279872.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63AB1QqD1322636\n for ; Fri, 10 Apr 2026 17:56:12 GMT","from mail-dl1-f71.google.com (mail-dl1-f71.google.com\n [74.125.82.71])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4deyyh98ga-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Fri, 10 Apr 2026 17:56:12 +0000 (GMT)","by mail-dl1-f71.google.com with SMTP id\n a92af1059eb24-12711ec96fbso3874340c88.0\n for ; Fri, 10 Apr 2026 10:56:12 -0700 (PDT)","from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com.\n [129.46.96.20]) by smtp.gmail.com with ESMTPSA id\n a92af1059eb24-12c3459f7ffsm4256271c88.3.2026.04.10.10.56.09\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 10 Apr 2026 10:56:10 -0700 (PDT)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n cc:content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=qcppdkim1; bh=Deo326n2qmw\n FTkLiBkqpjqgcq8M3rSAS5nM+pXYoWxY=; b=hsB2mEdkGoP9clcksHN4hyd+zWf\n U3lm3YRXhhCUDS/JD72WVMHnF4tyCX54rbxGN8Wu0lITYhpHWwAd1LXqeTVhoih8\n sYBWgYNw0j1Mcwk38aPs5eGjG/Iuu0HHG1vrev/fK29Zv5iLZ7hXdJz3IF0d47Ql\n KglH+N6wQ0pEt9hVQldchMPq+DuSLM2OF0tX9ZQP26X28yBOzBPDNp3+4ttM9OQL\n ZJxc6OG/Oj4/ypi3OEqh/hrTLajBLI0WP7669UVSr3pWIZ4aqRsFf9zoVP0oGNfM\n h1VSbYwNnWnNP6LfZlRWP/svWiqsW5uqlm3TIX6fg+KU+lnLeoWdqMZfQEA==","v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775843771; x=1776448571; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=Deo326n2qmwFTkLiBkqpjqgcq8M3rSAS5nM+pXYoWxY=;\n b=VGR/dt1G3oq3paHz0KB4EjvhtnDep7x7SABY3y23MwO+aeloDzB5Z7wNesjiRWvZWh\n d+UDJu1tyVj9e2iPVLYyMasgxsLmJuQJ3wlNb4IFOyF6+H9nJcwAN8hQhK2Gp4gCDbOW\n hnKkVf/nKM5bHWnfYiYGZ2DhkwE6wVuQqzn+t/VDoBREthmCHgrdRz0DDnXRydYMrwA7\n pm20gFFF1cJPqxL1fieJcTelyRY3rZSFHQs03fQzsDxmLAhCUYhZ0kLwZaeLuyjIu0b7\n rmSTsmAt/ktXjjLzh/bQWXnq9ZFG4wNbMxNxYmGZQMdGmLmws6uA2/lqkOt3/nvTuZnv\n tBqg=="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775843771; x=1776448571;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=Deo326n2qmwFTkLiBkqpjqgcq8M3rSAS5nM+pXYoWxY=;\n b=GBYOINC6VEvd7NkMSilR9NkKVLwNpgcNqcYJ8JcqJ8zmY/IvraB27zaDfNFzd9Gi6s\n g0QZCFfl0tLjhIUg1OL/XPD585Y97AEFIEgxjqAHcsxnFc16cECDp3I7hIT+eSLkV3mo\n TVF3c0sSk1fz7vsD7zTZ8vuklWX/CJJu1qwwlkKjIcMS3Fj6J5sIgkzx+qSReQ+cKpAF\n Cp22kyprttxytal78ydquxD+WmOyw+vNuceEnjm1+fFKFje3yfq3z73SIq8upbCZHGUa\n kLWDtx0a9Oz1z6DrTaX2tr1ZOAPeKeV04mQl1AOITcK27d/CFcD6jKT7YSAF/qKNLks/\n uZBg==","X-Gm-Message-State":"AOJu0YwCE0tVjJtT4ZsHkvO0kM8i16wCQuhPMC9t8ZsKwpOOJEaN1yMJ\n SkW4TYqWFqo4I9exE0A9qRi6cQp1GHqrrNCec1PAAzlcLUbfLc56joGiblLIMRgZE1GjGT48RMZ\n KIJojQ/Uf4otJK1hQYxY4RlAQvhlALjF+pBTKiK1M1CfB/VjZvMXWSXT5+mIzO50m4yaO","X-Gm-Gg":"AeBDieuthnq+RS2cX3HJAcG+kNr3Bud56HrgqHaaXmyufzfbzVjTMWPTX0K1xnnGal2\n ZYNGYuMcUtV3f78IOD26zXmUyZNhWPNvgd/TIsffFyMFyuqzTXOhLL4Yk8j0LHMxlSIdbrVo11m\n XEr1JOhdXAX3P2nRVaHiue1x025yT7s4YGCocJQuCH88tyxUKxIdAXWyQMshAWFLFHwd88n5gsb\n Z+0EKVMSQ9ZmvoSx5T6W5r4quI+xVy2yZayySsErpzk+FzXTy9g+s4B7x4Za3XWIC4NjfLbvogn\n hp0gYdAubvCrBnMhXBv2/9OoYIa8GTt/ISKJh04Rb2jYzBTkHfLr6gQpxurMykDrsXAlZCoBpJa\n KKzFbS/phl6gaiDyXzRHhqoCUjc+kDR3t4vfGsaOYFQyki6bDc8DwKOTXt0XpGyU+y7F9DwsKQN\n dR/Y8VLoiy","X-Received":["by 2002:a05:7022:321:b0:12b:f616:1a35 with SMTP id\n a92af1059eb24-12c34ea90e7mr2456173c88.8.1775843771279;\n Fri, 10 Apr 2026 10:56:11 -0700 (PDT)","by 2002:a05:7022:321:b0:12b:f616:1a35 with SMTP id\n a92af1059eb24-12c34ea90e7mr2456156c88.8.1775843770652;\n Fri, 10 Apr 2026 10:56:10 -0700 (PDT)"],"From":"Matheus Tavares Bernardino ","To":"qemu-devel@nongnu.org","Cc":"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com","Subject":"[PATCH v4 04/16] hexagon: group cpu configurations in their own\n struct","Date":"Fri, 10 Apr 2026 10:55:52 -0700","Message-Id":"\n ","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDEwMDE2OCBTYWx0ZWRfX2Z1+rajOIF7v\n Zj9SVO78ZoDFybJZOtZcJ3WtEfZ2dOhTIUzOEkv06b4Le2npy3MS3Btslwsc+hm3qMlOikli0gE\n eRx2Z+z98opQAhujVwnEFI0Xix+HOdMAR6fLTQpmtd//l/CDXBa467MBXfm5GIl7rsQLrHue2n9\n AbwmixH0c8yHStV492pzY2F44v6cwpvfjWw6UpQwhh3fqVuSe6GgwIpofziJDIf8ne/zS5MedbQ\n AqqePPRa+4ZaKYtQHS3hG3RJV7R5RsqUDYJIQagxKg3zjqj+jBP8hIqpDLEwLW0WbmVNXHc8hN1\n iJo0tjNWyNxnTP+ZFmOV6lR1Gb4y2LGg0sLL8Df6YayVuZEkYwKgXUuq8V2ujLS+7+KqxXMEq4M\n 9aYhHfZnwWkSiHtlht3/1BjJjZe7GGwYe7JdceUWOoJJ/pOKVr0srHHpErt83oUASsR1/hwgbbn\n 30VZ2vz7TmVyQmo271w==","X-Proofpoint-GUID":"X6YTbxkQuSTof6k4ir3MV-HG1fXsbeY_","X-Proofpoint-ORIG-GUID":"X6YTbxkQuSTof6k4ir3MV-HG1fXsbeY_","X-Authority-Analysis":"v=2.4 cv=Wv8b99fv c=1 sm=1 tr=0 ts=69d939bc cx=c_pps\n a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=pGLkceISAAAA:8\n a=EUspDBNiAAAA:8 a=AHWWR7nXwgbOQO2z_T8A:9 a=Fk4IpSoW4aLDllm1B1p-:22","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-10_05,2026-04-09_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n malwarescore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0\n bulkscore=0 spamscore=0 phishscore=0 clxscore=1015 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100168","Received-SPF":"pass client-ip=205.220.180.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0b-0031df01.pphosted.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This will be used in a follow up commit.\n\nReviewed-by: Taylor Simpson \nSigned-off-by: Matheus Tavares Bernardino \n---\n target/hexagon/cpu.h | 10 +++-------\n target/hexagon/cpu_bits.h | 7 +++++++\n target/hexagon/cpu.c | 14 +++++++-------\n target/hexagon/translate.c | 6 +++---\n 4 files changed, 20 insertions(+), 17 deletions(-)","diff":"diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 77822a48b6..d28beaa92f 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -119,19 +119,15 @@ typedef struct HexagonCPUClass {\n ResettablePhases parent_phases;\n } HexagonCPUClass;\n \n+#include \"cpu_bits.h\"\n+\n struct ArchCPU {\n CPUState parent_obj;\n \n CPUHexagonState env;\n-\n- bool lldb_compat;\n- target_ulong lldb_stack_adjust;\n- bool short_circuit;\n- bool ieee_fp_extension;\n+ HexagonCPUConfig cfg;\n };\n \n-#include \"cpu_bits.h\"\n-\n FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)\n \n G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,\ndiff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h\nindex 19beca81c0..83d13de569 100644\n--- a/target/hexagon/cpu_bits.h\n+++ b/target/hexagon/cpu_bits.h\n@@ -20,6 +20,13 @@\n \n #include \"qemu/bitops.h\"\n \n+typedef struct HexagonCPUConfig {\n+ bool lldb_compat;\n+ uint32_t lldb_stack_adjust;\n+ bool short_circuit;\n+ bool ieee_fp_extension;\n+} HexagonCPUConfig;\n+\n #define PCALIGN 4\n #define PCALIGN_MASK (PCALIGN - 1)\n \ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 8b72a5d3c8..5470d9c7ce 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -50,11 +50,11 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)\n }\n \n static const Property hexagon_cpu_properties[] = {\n- DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, lldb_compat, false),\n- DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, lldb_stack_adjust, 0,\n- qdev_prop_uint32, target_ulong),\n- DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, short_circuit, true),\n- DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, ieee_fp_extension, true),\n+ DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, cfg.lldb_compat, false),\n+ DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, cfg.lldb_stack_adjust,\n+ 0, qdev_prop_uint32, target_ulong),\n+ DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, cfg.short_circuit, true),\n+ DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, cfg.ieee_fp_extension, true),\n };\n \n const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n@@ -77,7 +77,7 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)\n {\n HexagonCPU *cpu = env_archcpu(env);\n- target_ulong stack_adjust = cpu->lldb_stack_adjust;\n+ target_ulong stack_adjust = cpu->cfg.lldb_stack_adjust;\n target_ulong stack_start = env->stack_start;\n target_ulong stack_size = 0x10000;\n \n@@ -181,7 +181,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)\n {\n HexagonCPU *cpu = env_archcpu(env);\n \n- if (cpu->lldb_compat) {\n+ if (cpu->cfg.lldb_compat) {\n /*\n * When comparing with LLDB, it doesn't step through single-cycle\n * hardware loops the same way. So, we just skip them here\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex fa8f615a9e..ce3af96675 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -987,8 +987,8 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->num_hvx_insns = 0;\n ctx->branch_cond = TCG_COND_NEVER;\n ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);\n- ctx->short_circuit = hex_cpu->short_circuit;\n- ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension;\n+ ctx->short_circuit = hex_cpu->cfg.short_circuit;\n+ ctx->ieee_fp_extension = hex_cpu->cfg.ieee_fp_extension;\n }\n \n static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n@@ -1041,7 +1041,7 @@ static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)\n * so end the TLB after every packet.\n */\n HexagonCPU *hex_cpu = env_archcpu(env);\n- if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {\n+ if (hex_cpu->cfg.lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {\n ctx->base.is_jmp = DISAS_TOO_MANY;\n }\n }\n","prefixes":["v4","04/16"]}