{"id":2222048,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222048/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e24b76d95a5e7f45b8ca2fff8c89df89a1f4ac60.1775843299.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<e24b76d95a5e7f45b8ca2fff8c89df89a1f4ac60.1775843299.git.matheus.bernardino@oss.qualcomm.com>","date":"2026-04-10T17:55:53","name":"[v4,05/16] hexagon: print info on \"-d in_asm\" for disabled IEEE FP instructions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5d1a65b97b7ce65a23dd36a106807392b7908d3e","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/1.1/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e24b76d95a5e7f45b8ca2fff8c89df89a1f4ac60.1775843299.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":499491,"url":"http://patchwork.ozlabs.org/api/1.1/series/499491/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499491","date":"2026-04-10T17:55:50","name":"hexagon: add missing HVX float instructions","version":4,"mbox":"http://patchwork.ozlabs.org/series/499491/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222048/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222048/checks/","tags":{},"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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05/16] hexagon: print info on \"-d in_asm\" for disabled IEEE\n FP instructions","Date":"Fri, 10 Apr 2026 10:55:53 -0700","Message-Id":"\n <e24b76d95a5e7f45b8ca2fff8c89df89a1f4ac60.1775843299.git.matheus.bernardino@oss.qualcomm.com>","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"<cover.1775843299.git.matheus.bernardino@oss.qualcomm.com>","References":"<cover.1775843299.git.matheus.bernardino@oss.qualcomm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Authority-Analysis":"v=2.4 cv=Vs4Txe2n c=1 sm=1 tr=0 ts=69d939bd cx=c_pps\n a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=pGLkceISAAAA:8\n a=EUspDBNiAAAA:8 a=uwSgyZDXI7pCxt1u4dUA:9 a=vr4QvYf-bLy2KjpDp97w:22","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDEwMDE2OCBTYWx0ZWRfX8tPrXJEFZIKJ\n VTyVw9A4kPdkxZpWgEVMhMg+y/laH5+0mazohCAzSQz4svr/maIPl+D3Ri0KiRPMAgDt0pBHdp7\n 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<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"When cpu->cfg.ieee_fp_extension is off, IEEE FP instructions don't get\nexecuted. Let's print that info on the \"-d in_asm\" output to help users.\nThis will generate an output like the following:\n\n0x00020e30:  0x1f82e1c0 {       V0.sf = vadd(V1.sf,V2.sf) (disabled: no ieee_fp) }\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/cpu_bits.h  | 3 ++-\n target/hexagon/printinsn.h | 2 +-\n disas/hexagon.c            | 3 ++-\n target/hexagon/cpu.c       | 2 ++\n target/hexagon/decode.c    | 4 ++--\n target/hexagon/printinsn.c | 7 ++++++-\n 6 files changed, 15 insertions(+), 6 deletions(-)","diff":"diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h\nindex 83d13de569..1f9e617d72 100644\n--- a/target/hexagon/cpu_bits.h\n+++ b/target/hexagon/cpu_bits.h\n@@ -72,6 +72,7 @@ static inline bool is_packet_end(uint32_t endocing)\n     return ((bits == 0x3) || (bits == 0x0));\n }\n \n-int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, GString *buf);\n+int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,\n+                        GString *buf, const HexagonCPUConfig *cfg);\n \n #endif\ndiff --git a/target/hexagon/printinsn.h b/target/hexagon/printinsn.h\nindex 2ecd1731d0..6a45ec571f 100644\n--- a/target/hexagon/printinsn.h\n+++ b/target/hexagon/printinsn.h\n@@ -21,7 +21,7 @@\n #include \"insn.h\"\n \n void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,\n-                         target_ulong pc);\n+                         target_ulong pc, const HexagonCPUConfig *cfg);\n void snprint_a_pkt_debug(GString *buf, Packet *pkt);\n \n #endif\ndiff --git a/disas/hexagon.c b/disas/hexagon.c\nindex c1a4ffc5f6..e2d3804606 100644\n--- a/disas/hexagon.c\n+++ b/disas/hexagon.c\n@@ -57,8 +57,9 @@ int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)\n         return PACKET_WORDS_MAX * sizeof(uint32_t);\n     }\n \n+    const HexagonCPUConfig *cfg = info->target_info;\n     buf = g_string_sized_new(PACKET_BUFFER_LEN);\n-    len = disassemble_hexagon(words, i, memaddr, buf);\n+    len = disassemble_hexagon(words, i, memaddr, buf, cfg);\n     (*info->fprintf_func)(info->stream, \"%s\", buf->str);\n     g_string_free(buf, true);\n \ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 5470d9c7ce..d7f4df5f96 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -307,6 +307,8 @@ static void hexagon_cpu_disas_set_info(const CPUState *cs,\n {\n     info->print_insn = print_insn_hexagon;\n     info->endian = BFD_ENDIAN_LITTLE;\n+    HexagonCPU *cpu = HEXAGON_CPU(cs);\n+    info->target_info = &cpu->cfg;\n }\n \n static void hexagon_cpu_realize(DeviceState *dev, Error **errp)\ndiff --git a/target/hexagon/decode.c b/target/hexagon/decode.c\nindex dbc9c630e8..d7ce8c8e1b 100644\n--- a/target/hexagon/decode.c\n+++ b/target/hexagon/decode.c\n@@ -801,7 +801,7 @@ int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,\n \n /* Used for \"-d in_asm\" logging */\n int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,\n-                        GString *buf)\n+                        GString *buf, const HexagonCPUConfig *cfg)\n {\n     DisasContext ctx;\n     Packet pkt;\n@@ -810,7 +810,7 @@ int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,\n     ctx.pkt = &pkt;\n \n     if (decode_packet(&ctx, nwords, words, &pkt, true) > 0) {\n-        snprint_a_pkt_disas(buf, &pkt, words, pc);\n+        snprint_a_pkt_disas(buf, &pkt, words, pc, cfg);\n         return pkt.encod_pkt_size_in_bytes;\n     } else {\n         g_string_assign(buf, \"<invalid>\");\ndiff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c\nindex 4865cdd133..85527f56e2 100644\n--- a/target/hexagon/printinsn.c\n+++ b/target/hexagon/printinsn.c\n@@ -51,7 +51,7 @@ static void snprintinsn(GString *buf, Insn *insn)\n }\n \n void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,\n-                         target_ulong pc)\n+                         target_ulong pc, const HexagonCPUConfig *cfg)\n {\n     bool has_endloop0 = false;\n     bool has_endloop1 = false;\n@@ -85,6 +85,11 @@ void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,\n         g_string_append(buf, \"\\t\");\n         snprintinsn(buf, &(pkt->insn[i]));\n \n+        if (!cfg->ieee_fp_extension &&\n+            GET_ATTRIB(pkt->insn[i].opcode, A_HVX_IEEE_FP)) {\n+            g_string_append(buf, \" (disabled: no ieee_fp)\");\n+        }\n+\n         if (i < pkt->num_insns - 1) {\n             /*\n              * Subinstructions are two instructions encoded\n","prefixes":["v4","05/16"]}