{"id":2222046,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2222046/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/b9a5a46b82e804d3c1cbeff678a9871a2b25a900.1775843299.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"","date":"2026-04-10T17:55:50","name":"[v4,02/16] target/hexagon: fix incorrect/too-permissive HVX encodings","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"97569ab9c624c31f26962cdf193fd72b5d956685","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/1.1/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/b9a5a46b82e804d3c1cbeff678a9871a2b25a900.1775843299.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":499491,"url":"http://patchwork.ozlabs.org/api/1.1/series/499491/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499491","date":"2026-04-10T17:55:50","name":"hexagon: add missing HVX float instructions","version":4,"mbox":"http://patchwork.ozlabs.org/series/499491/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2222046/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2222046/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com 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autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The following encodings have become stricter since v68:\n\n - V6_vunpackob, V6_vunpackoh: ---00 -> --000\n - V6_vaddbq/hq/wq, V6_vaddbnq/hnq/wnq: ---01 -> --001\n - V6_vsubbq/hq, V6_vsubwq/bnq/hnq/wnq: ---01/---10 -> --001/--010\n - V6_vhist, V6_vwhist128/256, V6_vwhist128/256_sat: ---00 -> --000\n - V6_vhistq, V6_vwhist128/256q, V6_vwhist128/256q_sat: ---10 -> --010\n\nPre v68 compilers, by default, already use \"0\" for the non-specified bit\nthat changed in v68, so unless someone is manually writing the binary\nencoding, this should not cause any backwards incompatibility with\npre-v68 binaries.\n\nReviewed-by: Taylor Simpson \nSigned-off-by: Matheus Tavares Bernardino \n---\n target/hexagon/imported/mmvec/encode_ext.def | 48 ++++++++++----------\n 1 file changed, 24 insertions(+), 24 deletions(-)","diff":"diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 402438f566..6d70086b5f 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -647,36 +647,36 @@ DEF_ENC(V6_vsubububb_sat, ICLASS_CJ\" 1 110 101 vvvvv PP 0 uuuuu 101 ddddd\")\n DEF_ENC(V6_vmpyewuh_64, ICLASS_CJ\" 1 110 101 vvvvv PP 0 uuuuu 110 ddddd\")\n \n DEF_FIELDROW_DESC32( ICLASS_CJ\" 1 110 --0 ----- PP 1 ----- ----- ---\",\"Vx32=Vu32\")\n-DEF_ENC(V6_vunpackob, ICLASS_CJ\" 1 110 --0 ---00 PP 1 uuuuu 000 xxxxx\") //\n-DEF_ENC(V6_vunpackoh, ICLASS_CJ\" 1 110 --0 ---00 PP 1 uuuuu 001 xxxxx\") //\n+DEF_ENC(V6_vunpackob, ICLASS_CJ\" 1 110 --0 --000 PP 1 uuuuu 000 xxxxx\") //\n+DEF_ENC(V6_vunpackoh, ICLASS_CJ\" 1 110 --0 --000 PP 1 uuuuu 001 xxxxx\") //\n //DEF_ENC(V6_vunpackow, ICLASS_CJ\" 1 110 --0 ---00 PP 1 uuuuu 010 xxxxx\") //\n \n-DEF_ENC(V6_vhist, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -000- 100 -----\")\n-DEF_ENC(V6_vwhist256, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -0010 100 -----\")\n-DEF_ENC(V6_vwhist256_sat, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -0011 100 -----\")\n-DEF_ENC(V6_vwhist128, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -010- 100 -----\")\n-DEF_ENC(V6_vwhist128m, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -011i 100 -----\")\n+DEF_ENC(V6_vhist, ICLASS_CJ\" 1 110 --0 --000 PP 1 -000- 100 -----\")\n+DEF_ENC(V6_vwhist256, ICLASS_CJ\" 1 110 --0 --000 PP 1 -0010 100 -----\")\n+DEF_ENC(V6_vwhist256_sat, ICLASS_CJ\" 1 110 --0 --000 PP 1 -0011 100 -----\")\n+DEF_ENC(V6_vwhist128, ICLASS_CJ\" 1 110 --0 --000 PP 1 -010- 100 -----\")\n+DEF_ENC(V6_vwhist128m, ICLASS_CJ\" 1 110 --0 --000 PP 1 -011i 100 -----\")\n \n DEF_FIELDROW_DESC32( ICLASS_CJ\" 1 110 --0 ----- PP 1 ----- ----- ---\",\"if (Qv4) Vx32=Vu32\")\n-DEF_ENC(V6_vaddbq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 000 xxxxx\") //\n-DEF_ENC(V6_vaddhq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 001 xxxxx\") //\n-DEF_ENC(V6_vaddwq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 010 xxxxx\") //\n-DEF_ENC(V6_vaddbnq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 011 xxxxx\") //\n-DEF_ENC(V6_vaddhnq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 100 xxxxx\") //\n-DEF_ENC(V6_vaddwnq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 101 xxxxx\") //\n-DEF_ENC(V6_vsubbq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 110 xxxxx\") //\n-DEF_ENC(V6_vsubhq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 111 xxxxx\") //\n+DEF_ENC(V6_vaddbq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 000 xxxxx\") //\n+DEF_ENC(V6_vaddhq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 001 xxxxx\") //\n+DEF_ENC(V6_vaddwq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 010 xxxxx\") //\n+DEF_ENC(V6_vaddbnq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 011 xxxxx\") //\n+DEF_ENC(V6_vaddhnq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 100 xxxxx\") //\n+DEF_ENC(V6_vaddwnq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 101 xxxxx\") //\n+DEF_ENC(V6_vsubbq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 110 xxxxx\") //\n+DEF_ENC(V6_vsubhq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 111 xxxxx\") //\n \n-DEF_ENC(V6_vsubwq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 uuuuu 000 xxxxx\") //\n-DEF_ENC(V6_vsubbnq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 uuuuu 001 xxxxx\") //\n-DEF_ENC(V6_vsubhnq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 uuuuu 010 xxxxx\") //\n-DEF_ENC(V6_vsubwnq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 uuuuu 011 xxxxx\") //\n+DEF_ENC(V6_vsubwq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 uuuuu 000 xxxxx\") //\n+DEF_ENC(V6_vsubbnq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 uuuuu 001 xxxxx\") //\n+DEF_ENC(V6_vsubhnq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 uuuuu 010 xxxxx\") //\n+DEF_ENC(V6_vsubwnq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 uuuuu 011 xxxxx\") //\n \n-DEF_ENC(V6_vhistq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --00- 100 -----\")\n-DEF_ENC(V6_vwhist256q, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --010 100 -----\")\n-DEF_ENC(V6_vwhist256q_sat, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --011 100 -----\")\n-DEF_ENC(V6_vwhist128q, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --10- 100 -----\")\n-DEF_ENC(V6_vwhist128qm, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --11i 100 -----\")\n+DEF_ENC(V6_vhistq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --00- 100 -----\")\n+DEF_ENC(V6_vwhist256q, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --010 100 -----\")\n+DEF_ENC(V6_vwhist256q_sat, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --011 100 -----\")\n+DEF_ENC(V6_vwhist128q, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --10- 100 -----\")\n+DEF_ENC(V6_vwhist128qm, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --11i 100 -----\")\n \n \n DEF_ENC(V6_vandvqv, ICLASS_CJ\" 1 110 vv0 ---11 PP 1 uuuuu 000 ddddd\")\n","prefixes":["v4","02/16"]}