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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n AM3PEPF00009B9C.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"The pattern expands usubc(diff, Bout, x, y, Bin into:\nnegs Bin\nsbcs diff, x, y\ncset Bout, cc\n\nIt also tries to fold if y, or Bin are constants:\n\nIf Bin != 0, Y = ~0:\nmov diff, x\nmov Bout, 1\n\nIf Bin = 0, Y = 0:\nmov diff, x\nmov Bout, 0\n\nSimilar to the chained uaddc, chained usubc expansions results in a round trip\nCC -> register -> CC. Remove that round-trip as CSET-like materialization does\nnot clobber flags, so CC already carries the same bit.\n\ngcc/ChangeLog:\n\n\tPR target/122525\n\t* config/aarch64/aarch64.md\n\t(usubc5): Expansion pattern for usubc5.\n\t(*aarch64_setc_from_borrow_) Post-combine no-op split\n\tpattern for carry chain elimination.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/usubc-builtin-sub-overflow.c: New test\n\tchained usubc expansion for __builtin_usubc_overflow.\n\t* gcc.target/aarch64/usubc-builtin-subc.c: New test for\n\t__builtin_subc.\n\t* gcc.target/aarch64/usubc-builtin-subcl.c: New test for\n\t__builtin_subcl.\n\t* gcc.target/aarch64/usubc-const-minus1.c: New test for\n\tusubc where y = ~0.\n\t* gcc.target/aarch64/usubc-const-plus1.c: New test for\n\tusubc where y is constant.\n---\n gcc/config/aarch64/aarch64.md | 89 +++++++++++++++++++\n .../aarch64/usubc-builtin-sub-overflow.c | 28 ++++++\n .../gcc.target/aarch64/usubc-builtin-subc.c | 17 ++++\n .../gcc.target/aarch64/usubc-builtin-subcl.c | 17 ++++\n .../gcc.target/aarch64/usubc-const-minus1.c | 14 +++\n .../gcc.target/aarch64/usubc-const-plus1.c | 12 +++\n 6 files changed, 177 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-builtin-sub-overflow.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-builtin-subc.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-builtin-subcl.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-const-minus1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-const-plus1.c","diff":"diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 3fd476f838f..75aa4e893c6 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -4111,6 +4111,95 @@ (define_insn \"*subsi3_carryin_alt_uxtw\"\n [(set_attr \"type\" \"adc_reg\")]\n )\n \n+(define_expand \"usubc5\"\n+ [(match_operand:GPI 0 \"register_operand\") ;; difference\n+ (match_operand:GPI 1 \"register_operand\") ;; borrow-out\n+ (match_operand:GPI 2 \"register_operand\") ;; x\n+ (match_operand:GPI 3 \"nonmemory_operand\") ;; y\n+ (match_operand:GPI 4 \"nonmemory_operand\")] ;; borrow-in\n+ \"\"\n+{\n+ if (operands[4] == const0_rtx)\n+ {\n+ rtx y = operands[3];\n+ if (aarch64_reg_or_zero (y, mode))\n+\temit_insn (gen_sub3_compare1 (operands[0], operands[2], y));\n+ else if (CONST_SCALAR_INT_P (y) && aarch64_plus_immediate (y, mode))\n+\t{\n+\t rtx minus_y = immed_wide_int_const (wi::neg (\n+\t\t\t\t\t rtx_mode_t (y, mode)),\n+\t\t\t\t\t mode);\n+\t emit_insn (gen_sub3_compare1_imm (operands[0], operands[2],\n+\t\t\t\t\t\t y, minus_y));\n+\t}\n+ else\n+\t{\n+\t y = force_reg (mode, y);\n+\t emit_insn (gen_sub3_compare1 (operands[0], operands[2], y));\n+\t}\n+ }\n+ else if (CONST_SCALAR_INT_P (operands[4]))\n+ {\n+ if (operands[3] == constm1_rtx)\n+\t{\n+\t emit_move_insn (operands[0], operands[2]);\n+\t emit_move_insn (operands[1], const1_rtx);\n+\t DONE;\n+\t}\n+ else\n+\t{\n+\t rtx rhs = plus_constant (mode, operands[3], 1);\n+\t if (aarch64_reg_or_zero (rhs, mode))\n+\t emit_insn (gen_sub3_compare1 (operands[0], operands[2], rhs));\n+\t else if (CONST_SCALAR_INT_P (rhs)\n+\t\t && aarch64_plus_immediate (rhs, mode))\n+\t {\n+\t rtx minus_rhs\n+\t\t= immed_wide_int_const (wi::neg (rtx_mode_t (rhs, mode)),\n+\t\t\t\t\tmode);\n+\t emit_insn (gen_sub3_compare1_imm (operands[0], operands[2],\n+\t\t\t\t\t\t rhs, minus_rhs));\n+\t }\n+\t else\n+\t {\n+\t rhs = force_reg (mode, rhs);\n+\t emit_insn (gen_sub3_compare1 (operands[0],\n+\t\t\t\t\t\t operands[2],\n+\t\t\t\t\t\t rhs));\n+\t }\n+\t}\n+ }\n+ else\n+ {\n+ rtx cin = force_reg (mode, operands[4]);\n+ rtx tmp = gen_reg_rtx (mode);\n+ rtx y = operands[3];\n+ if (!register_operand (y, mode))\n+\ty = force_reg (mode, y);\n+ emit_insn (gen_sub3_compare1 (tmp, const0_rtx, cin));\n+ emit_insn (gen_usub3_carryinC (operands[0], operands[2],\n+\t\t\t\t\t y));\n+ }\n+ rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);\n+ rtx pat = gen_rtx_GEU (mode, cc, const0_rtx);\n+ emit_insn (gen_rtx_SET (operands[1], pat));\n+ DONE;\n+})\n+\n+;; Similar to the chained uaddc, chained usubc expansions results in a round\n+;; trip CC -> register -> CC. Remove that round-trip as CSET-like\n+;; materialization does not clobber flags, so CC already carries the same bit.\n+(define_insn_and_split \"*aarch64_setc_from_borrow_\"\n+ [(set (reg:CC CC_REGNUM)\n+\t(compare:CC\n+\t (const_int 0)\n+\t (match_operand:GPI 0 \"aarch64_borrow_operation\" \"\")))]\n+ \"\"\n+ \"#\"\n+ \"\"\n+ [(const_int 0)]\n+ \"emit_note (NOTE_INSN_DELETED); DONE;\")\n+\n (define_expand \"usub3_carryinC\"\n [(parallel\n [(set (reg:CC CC_REGNUM)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-builtin-sub-overflow.c b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-sub-overflow.c\nnew file mode 100644\nindex 00000000000..2e4b7c311d3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-sub-overflow.c\n@@ -0,0 +1,28 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+static unsigned long\n+usubc (unsigned long x, unsigned long y, unsigned long carry_in,\n+ unsigned long *carry_out)\n+{\n+ unsigned long r;\n+ unsigned long c1 = __builtin_sub_overflow (x, y, &r);\n+ unsigned long c2 = __builtin_sub_overflow (r, carry_in, &r);\n+ *carry_out = c1 + c2;\n+ return r;\n+}\n+\n+void __attribute__ ((__noinline__))\n+bar (unsigned long *p, unsigned long *q)\n+{\n+ unsigned long c;\n+ p[0] = usubc (p[0], q[0], 0, &c);\n+ p[1] = usubc (p[1], q[1], c, &c);\n+ p[2] = usubc (p[2], q[2], c, &c);\n+ p[3] = usubc (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"sbcs\\\\t\\[xw\\]\\[0-9\\]+, \\[xw\\]\\[0-9\\]+,\n+ * \\[xw\\]\\[0-9\\]+\" 3 } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\t\\[xw\\]\\[0-9\\]+, cc+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subc.c b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subc.c\nnew file mode 100644\nindex 00000000000..6279aa3fd83\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subc.c\n@@ -0,0 +1,17 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+void\n+bar (unsigned int *p, unsigned int *q)\n+{\n+ unsigned int c;\n+ p[0] = __builtin_subc (p[0], q[0], 0, &c);\n+ p[1] = __builtin_subc (p[1], q[1], c, &c);\n+ p[2] = __builtin_subc (p[2], q[2], c, &c);\n+ p[3] = __builtin_subc (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"sbcs\\\\tw\\[0-9\\]+, w\\[0-9\\]+, w\\[0-9\\]+\" 3\n+ * } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\tw\\[0-9\\]+, cc+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subcl.c b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subcl.c\nnew file mode 100644\nindex 00000000000..4792afba4f0\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subcl.c\n@@ -0,0 +1,17 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+void\n+bar (unsigned long *p, unsigned long *q)\n+{\n+ unsigned long c;\n+ p[0] = __builtin_subcl (p[0], q[0], 0, &c);\n+ p[1] = __builtin_subcl (p[1], q[1], c, &c);\n+ p[2] = __builtin_subcl (p[2], q[2], c, &c);\n+ p[3] = __builtin_subcl (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"sbcs\\\\tx\\[0-9\\]+, x\\[0-9\\]+,\n+ * x\\[0-9\\]+\" 3 } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\tx\\[0-9\\]+, cc+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-const-minus1.c b/gcc/testsuite/gcc.target/aarch64/usubc-const-minus1.c\nnew file mode 100644\nindex 00000000000..0c9f94bb97d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-const-minus1.c\n@@ -0,0 +1,14 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+unsigned long\n+bar (unsigned long x, unsigned long *b)\n+{\n+ return __builtin_subcl (x, ~0UL, 1, b);\n+}\n+\n+/* { dg-final { scan-assembler-not \"subs\\\\t\" } } */\n+/* { dg-final { scan-assembler-not \"sbcs\\\\t\" } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\t\" } } */\n+/* { dg-final { scan-assembler \"mov\\\\tx\\[0-9\\]+, 1\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-const-plus1.c b/gcc/testsuite/gcc.target/aarch64/usubc-const-plus1.c\nnew file mode 100644\nindex 00000000000..d82a9ef6216\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-const-plus1.c\n@@ -0,0 +1,12 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+unsigned long\n+bar (unsigned long x, unsigned long *b)\n+{\n+ return __builtin_subcl (x, 41, 1, b);\n+}\n+\n+/* { dg-final { scan-assembler \"subs\\\\tx\\[0-9\\]+, x\\[0-9\\]+, 42\" } } */\n+/* { dg-final { scan-assembler-not \"sbcs\\\\t\" } } */\n","prefixes":["v4","3/3"]}