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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n DB3PEPF00008859.eurprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"The pattern expands uaddc(sum, Cout, x, y, Cin) into:\ncmp Cin, #1\nadcs sum, x, y\ncset Cout, cs\n\nThe expansion folds the additions if the operands are known at compile time:\n\nIf Cin = 0, y = 0:\nmov sum, x\nmov Cout, 0\n\nIf Cin != 0, y = ~0:\nmov sum, x\nmov Cout, 1\n\nCarry chained uaddc expansion results in a rount trip CC -> register -> CC.\nRemove that round-trip as CSET-like materialization does not clobber flags, so\nCC already carries the same bit.\n\ngcc/ChangeLog:\n\n\tPR target/122525\n\t* config/aarch64/aarch64.md\n\t(uaddc5): Expansion pattern for uaddc5.\n\t(*aarch64_setc_from_carry_) Post-combine no-op split pattern for\n\tcarry chain elimination in CC_Cmode.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/uaddc-builtin-add-overflow.c: New test for chained\n\tuaddc expansion for __builtin_add_overflow.\n\t* gcc.target/aarch64/uaddc-builtin-addc.c: New test chained uaddc\n\texpansion for __builtin_addc.\n\t* gcc.target/aarch64/uaddc-builtin-addcl.c: New test for uaddc expansion\n\tfor __builtin_addcl.\n\t* gcc.target/aarch64/uaddc-const-minus1.c: New test for uaddc expansion\n\twhere addend 2 is ~0.\n\t* gcc.target/aarch64/uaddc-const-plus1.c: New test for uaddc expansion\n\twhere addend 2 is a constant.\n---\n gcc/config/aarch64/aarch64.md | 80 +++++++++++++++++++\n .../aarch64/uaddc-builtin-add-overflow.c | 28 +++++++\n .../gcc.target/aarch64/uaddc-builtin-addc.c | 17 ++++\n .../gcc.target/aarch64/uaddc-builtin-addcl.c | 17 ++++\n .../gcc.target/aarch64/uaddc-const-minus1.c | 14 ++++\n .../gcc.target/aarch64/uaddc-const-plus1.c | 12 +++\n 6 files changed, 168 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-builtin-add-overflow.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addc.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addcl.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-const-minus1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-const-plus1.c","diff":"diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 744acac0290..3fd476f838f 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -3389,6 +3389,86 @@ (define_insn \"*add3_carryinC\"\n [(set_attr \"type\" \"adc_reg\")]\n )\n \n+(define_expand \"uaddc5\"\n+ [(match_operand:GPI 0 \"register_operand\") ;; sum\n+ (match_operand:GPI 1 \"register_operand\") ;; carry-out\n+ (match_operand:GPI 2 \"register_operand\") ;; x\n+ (match_operand:GPI 3 \"nonmemory_operand\") ;; y\n+ (match_operand:GPI 4 \"nonmemory_operand\")] ;; carry-in\n+ \"\"\n+{\n+ if (operands[4] == const0_rtx)\n+ {\n+ if (operands[3] == const0_rtx)\n+\t{\n+\t emit_move_insn (operands[0], operands[2]);\n+\t emit_move_insn (operands[1], const0_rtx);\n+\t}\n+ else\n+\t{\n+\t rtx y = operands[3];\n+\t if (!aarch64_plus_operand (y, mode))\n+\t y = force_reg (mode, y);\n+\t emit_insn (gen_add3_compareC (operands[0], operands[2], y));\n+\t rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);\n+\t rtx pat = gen_rtx_LTU (mode, cc, const0_rtx);\n+\t emit_insn (gen_rtx_SET (operands[1], pat));\n+\t}\n+ }\n+ else if (CONST_SCALAR_INT_P (operands[4]))\n+ {\n+ if (operands[3] == constm1_rtx)\n+\t{\n+\t emit_move_insn (operands[0], operands[2]);\n+\t emit_move_insn (operands[1], const1_rtx);\n+\t}\n+ else\n+\t{\n+\t rtx rhs = plus_constant (mode, operands[3], 1);\n+\t if (!aarch64_plus_operand (rhs, mode))\n+\t rhs = force_reg (mode, rhs);\n+\t emit_insn (gen_add3_compareC (operands[0], operands[2], rhs));\n+\t rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);\n+\t rtx pat = gen_rtx_LTU (mode, cc, const0_rtx);\n+\t emit_insn (gen_rtx_SET (operands[1], pat));\n+\t}\n+ }\n+ else\n+ {\n+ rtx cin = force_reg (mode, operands[4]);\n+ rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);\n+ rtx adc_cc = gen_rtx_REG (CC_ADCmode, CC_REGNUM);\n+ rtx y = operands[3];\n+ if (!register_operand (y, mode))\n+\ty = force_reg (mode, y);\n+ rtx cmp = gen_rtx_COMPARE (CC_Cmode,\n+\t\t\t\t gen_rtx_PLUS (mode, cin, constm1_rtx),\n+\t\t\t\t cin);\n+ emit_insn (gen_rtx_SET (cc, cmp));\n+ emit_insn (gen_add3_carryinC (operands[0], operands[2],\n+\t\t\t\t\t y));\n+ rtx pat = gen_rtx_GEU (mode, adc_cc, const0_rtx);\n+ emit_insn (gen_rtx_SET (operands[1], pat));\n+ }\n+ DONE;\n+})\n+\n+;; The uaddc expansion results in a round trip CC -> register -> CC. Remove\n+;; that round-trip as CSET-like materialization does not clobber flags, so CC\n+;; already carries the same bit.\n+;; With STORE_FLAG_VALUE == 1, simplify-rtx can canonicalize carry - 1 to\n+;; -!carry, where !carry is the complementary borrow-like test on the same CC.\n+(define_insn_and_split \"*aarch64_setc_from_carry_\"\n+ [(set (reg:CC_C CC_REGNUM)\n+\t(compare:CC_C\n+\t (neg:GPI (match_operand:GPI 0 \"aarch64_borrow_operation\" \"\"))\n+\t (match_operand:GPI 1 \"aarch64_carry_operation\" \"\")))]\n+ \"rtx_equal_p (XEXP (operands[0], 0), XEXP (operands[1], 0))\"\n+ \"#\"\n+ \"\"\n+ [(const_int 0)]\n+ \"emit_note (NOTE_INSN_DELETED); DONE;\")\n+\n (define_expand \"add3_carryinV\"\n [(parallel\n [(set (reg:CC_V CC_REGNUM)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-add-overflow.c b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-add-overflow.c\nnew file mode 100644\nindex 00000000000..ff8301973a8\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-add-overflow.c\n@@ -0,0 +1,28 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+static unsigned long\n+uaddc (unsigned long x, unsigned long y, unsigned long carry_in,\n+ unsigned long *carry_out)\n+{\n+ unsigned long r;\n+ unsigned long c1 = __builtin_add_overflow (x, y, &r);\n+ unsigned long c2 = __builtin_add_overflow (r, carry_in, &r);\n+ *carry_out = c1 + c2;\n+ return r;\n+}\n+\n+void\n+foo (unsigned long *p, unsigned long *q)\n+{\n+ unsigned long c;\n+ p[0] = uaddc (p[0], q[0], 0, &c);\n+ p[1] = uaddc (p[1], q[1], c, &c);\n+ p[2] = uaddc (p[2], q[2], c, &c);\n+ p[3] = uaddc (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"adcs\\\\t\\[xw\\]\\[0-9\\]+, \\[xw\\]\\[0-9\\]+,\n+\\[xw\\]\\[0-9\\]+\" 3 } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\t\\[xw\\]\\[0-9\\]+, cs+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addc.c b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addc.c\nnew file mode 100644\nindex 00000000000..ee28860c105\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addc.c\n@@ -0,0 +1,17 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+void\n+foo (unsigned int *p, unsigned int *q)\n+{\n+ unsigned int c;\n+ p[0] = __builtin_addc (p[0], q[0], 0, &c);\n+ p[1] = __builtin_addc (p[1], q[1], c, &c);\n+ p[2] = __builtin_addc (p[2], q[2], c, &c);\n+ p[3] = __builtin_addc (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"adcs\\\\tw\\[0-9\\]+, w\\[0-9\\]+, w\\[0-9\\]+\" 3\n+ * } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\tw\\[0-9\\]+, cs+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addcl.c b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addcl.c\nnew file mode 100644\nindex 00000000000..004d950f48c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addcl.c\n@@ -0,0 +1,17 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+void\n+foo (unsigned long *p, unsigned long *q)\n+{\n+ unsigned long c;\n+ p[0] = __builtin_addcl (p[0], q[0], 0, &c);\n+ p[1] = __builtin_addcl (p[1], q[1], c, &c);\n+ p[2] = __builtin_addcl (p[2], q[2], c, &c);\n+ p[3] = __builtin_addcl (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"adcs\\\\tx\\[0-9\\]+, x\\[0-9\\]+, x\\[0-9\\]+\" 3\n+ * } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\tx\\[0-9\\]+, cs+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-const-minus1.c b/gcc/testsuite/gcc.target/aarch64/uaddc-const-minus1.c\nnew file mode 100644\nindex 00000000000..48fbd5b8498\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-const-minus1.c\n@@ -0,0 +1,14 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+unsigned long\n+foo (unsigned long x, unsigned long *c)\n+{\n+ return __builtin_addcl (x, ~0UL, 1, c);\n+}\n+\n+/* { dg-final { scan-assembler-not \"adds\\\\t\" } } */\n+/* { dg-final { scan-assembler-not \"adcs\\\\t\" } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\t\" } } */\n+/* { dg-final { scan-assembler \"mov\\\\tx\\[0-9\\]+, 1\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-const-plus1.c b/gcc/testsuite/gcc.target/aarch64/uaddc-const-plus1.c\nnew file mode 100644\nindex 00000000000..d072f66525d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-const-plus1.c\n@@ -0,0 +1,12 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+unsigned long\n+foo (unsigned long x, unsigned long *c)\n+{\n+ return __builtin_addcl (x, 41, 1, c);\n+}\n+\n+/* { dg-final { scan-assembler \"adds\\\\tx\\[0-9\\]+, x\\[0-9\\]+, #42\" } } */\n+/* { dg-final { scan-assembler-not \"adcs\\\\t\" } } */\n","prefixes":["v4","2/3"]}