{"id":2221744,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221744/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260410083932.159741-1-lin1.hu@intel.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260410083932.159741-1-lin1.hu@intel.com>","date":"2026-04-10T08:39:32","name":"i386: Fix Intel syntax memory operand modifiers for AVX10.2 saturation conversions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6185fd5a3501a4370c36f977223c1f4f01c9a30e","submitter":{"id":87231,"url":"http://patchwork.ozlabs.org/api/1.1/people/87231/?format=json","name":"Hu, Lin1","email":"lin1.hu@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260410083932.159741-1-lin1.hu@intel.com/mbox/","series":[{"id":499424,"url":"http://patchwork.ozlabs.org/api/1.1/series/499424/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=499424","date":"2026-04-10T08:39:32","name":"i386: Fix Intel syntax memory operand modifiers for AVX10.2 saturation conversions","version":1,"mbox":"http://patchwork.ozlabs.org/series/499424/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221744/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221744/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=fbLtLbfV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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server2.sourceware.org","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775810378; x=1807346378;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=ajNU2sEKfRGmkuyoxkL6DViLAMP11AL+yujUbAy9JHI=;\n b=fbLtLbfVxsQa5hQTFysi3qUg0I+5wtSznfTnV7qj7PAbVGeS4Aj6Yz+4\n 6ZTIH/xywgLdphgnNSt6jwqhMvOVrLk/vx3QovfD39uGFrz730hWGbdQ1\n 2Ii1UUfpNUMRE7hA+08ws/kuR/Q5YJteZKlm5b17e0nduPf+6gEmcZ0Ci\n VhFkjOrLa8Cf0tqlCWWx6065CNguCDtS5G3+C1d68aN8KJK61SltH4Kze\n t6U4DVtVPu1dTs0vLRd97pVc+gB+WbvbO4NuSoN8F0LH0FVPm/w8FLSZN\n LX7rg24+c3lmpEJ/FQU6Up0dsJ9JRW5XAUp+czUjTnwSBlkLZ9SMlEAZS g==;","X-CSE-ConnectionGUID":["FKhI0imcROOf+1ylipUD7g==","jBb9D0pETEWu4a6G0c++zA=="],"X-CSE-MsgGUID":["dBMbr3jkT6KFNLz+Lo3cmw==","v0DAErmuQ0SHjZG9DAcCcw=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11754\"; a=\"76543445\"","E=Sophos;i=\"6.23,171,1770624000\"; d=\"scan'208\";a=\"76543445\"","E=Sophos;i=\"6.23,171,1770624000\"; d=\"scan'208\";a=\"228952573\""],"X-ExtLoop1":"1","From":"\"Hu, Lin1\" ","To":"gcc-patches@gcc.gnu.org","Cc":"hongtao.liu@intel.com,\n\tubizjak@gmail.com","Subject":"[PATCH] i386: Fix Intel syntax memory operand modifiers for AVX10.2\n saturation conversions","Date":"Fri, 10 Apr 2026 16:39:32 +0800","Message-Id":"<20260410083932.159741-1-lin1.hu@intel.com>","X-Mailer":"git-send-email 2.31.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"Hi,\n\nThe AVX10.2 saturation conversion instructions vcvttps2[u]qqs,\nvcvttsd2[u]sis and vcvttss2[u]sis are missing operand size modifiers in\ntheir Intel syntax output templates. This causes assembler errors when\nusing -masm=intel with memory operands, because Intel Syntax output\nwrong memory size.\n\nBootstrapped and regtested on x86-64-linux-pc-gnu, OK for trunk?\n\nBRs,\nLin\n\ngcc/ChangeLog:\n\n\tPR target/124710\n\t* config/i386/sse.md (iptrps2qq): New mode attribute for\n\tps2qq Intel syntax memory operand size override.\n\t(avx10_2_vcvttps2qqs):\n\tUse %1 in Intel syntax to emit qword ptr for V2DI (128-bit)\n\tmemory operands.\n\t(avx10_2_vcvttsd2sis):\n\tUse %q1 in Intel syntax to emit qword ptr for scalar double memory\n\toperands.\n\t(avx10_2_vcvttss2sis):\n\tUse %k1 in Intel syntax to emit dword ptr for scalar single memory\n\toperands.\n\ngcc/testsuite/ChangeLog:\n\n\tPR target/124710\n\t* gcc.target/i386/pr124710-1.c: New test.\n\t* gcc.target/i386/pr124710-2.c: Ditto.\n---\n gcc/config/i386/sse.md | 11 +++--\n gcc/testsuite/gcc.target/i386/pr124710-1.c | 16 ++++++\n gcc/testsuite/gcc.target/i386/pr124710-2.c | 57 ++++++++++++++++++++++\n 3 files changed, 81 insertions(+), 3 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/i386/pr124710-1.c\n create mode 100644 gcc/testsuite/gcc.target/i386/pr124710-2.c","diff":"diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md\nindex a3f68ad9c1a..7804269acb2 100644\n--- a/gcc/config/i386/sse.md\n+++ b/gcc/config/i386/sse.md\n@@ -33275,6 +33275,11 @@ (define_mode_attr pd2dqssuff\n [(V16SF \"\") (V8SF \"\") (V4SF \"\")\n (V8DF \"\") (V4DF \"{y}\") (V2DF \"{x}\")])\n \n+;; Pointer size override for ps2qq conversions: V2DI uses half-width (64-bit)\n+;; source, needing %q for Intel syntax memory operand disambiguation.\n+(define_mode_attr iptrps2qq\n+ [(V8DI \"\") (V4DI \"\") (V2DI \"q\")])\n+\n (define_insn \"avx10_2_vcvtt2dqs\"\n [(set (match_operand: 0 \"register_operand\" \"=v\")\n (unspec:\n@@ -33303,7 +33308,7 @@ (define_insn \"avx10_2_vcvttps2qqs 1 \"\" \"\")]\n \t UNSPEC_SAT_CVT_DS_SIGN_ITER))]\n \"TARGET_AVX10_2 && \"\n- \"vcvttps2qqs\\t{%1, %0|%0, %1}\"\n+ \"vcvttps2qqs\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"ssecvt\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"\")])\n@@ -33316,7 +33321,7 @@ (define_insn \"avx10_2_vcvttsd2sis\n (parallel [(const_int 0)]))]\n UNSPEC_SAT_CVT_DS_SIGN_ITER))]\n \"TARGET_AVX10_2\"\n- \"vcvttsd2sis\\t{%1, %0|%0, %1}\"\n+ \"vcvttsd2sis\\t{%1, %0|%0, %q1}\"\n [(set_attr \"type\" \"ssecvt\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"\")])\n@@ -33329,7 +33334,7 @@ (define_insn \"avx10_2_vcvttss2sis\n (parallel [(const_int 0)]))]\n UNSPEC_SAT_CVT_DS_SIGN_ITER))]\n \"TARGET_AVX10_2\"\n- \"vcvttss2sis\\t{%1, %0|%0, %1}\"\n+ \"vcvttss2sis\\t{%1, %0|%0, %k1}\"\n [(set_attr \"type\" \"ssecvt\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"\")])\ndiff --git a/gcc/testsuite/gcc.target/i386/pr124710-1.c b/gcc/testsuite/gcc.target/i386/pr124710-1.c\nnew file mode 100644\nindex 00000000000..aea176dffba\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/pr124710-1.c\n@@ -0,0 +1,16 @@\n+/* PR target/124710 */\n+/* { dg-do assemble } */\n+/* { dg-options \"-O -masm=intel -mavx10.2\" } */\n+/* { dg-require-effective-target masm_intel } */\n+/* { dg-require-effective-target avx10_2 } */\n+\n+#include \n+\n+__m128i v;\n+__m128 w;\n+\n+void\n+foo()\n+{\n+ v = _mm_mask_cvtts_ps_epi64(v, -1, w);\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/pr124710-2.c b/gcc/testsuite/gcc.target/i386/pr124710-2.c\nnew file mode 100644\nindex 00000000000..3d331448ef8\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/pr124710-2.c\n@@ -0,0 +1,57 @@\n+/* PR target/124710 */\n+/* { dg-do assemble } */\n+/* { dg-options \"-O2 -masm=intel -mavx10.2\" } */\n+/* { dg-require-effective-target masm_intel } */\n+/* { dg-require-effective-target avx10_2 } */\n+\n+typedef float __v4sf __attribute__ ((__vector_size__ (16)));\n+typedef double __v2df __attribute__ ((__vector_size__ (16)));\n+typedef long long __v2di __attribute__ ((__vector_size__ (16)));\n+\n+/* vcvttps2qqs 128-bit: source V4SF is half-width of dest V2DI,\n+ Intel syntax needs \"qword ptr\" for memory operand.\n+ At -O2 the compiler folds *p into the instruction. */\n+\n+__v2di\n+test_vcvttps2qqs128 (__v4sf *p)\n+{\n+ return (__v2di) __builtin_ia32_cvttps2qqs128_mask (*p, (__v2di) { 0, 0 },\n+\t\t\t\t\t\t (unsigned char) -1);\n+}\n+\n+__v2di\n+test_vcvttps2uqqs128 (__v4sf *p)\n+{\n+ return (__v2di) __builtin_ia32_cvttps2uqqs128_mask (*p, (__v2di) { 0, 0 },\n+\t\t\t\t\t\t (unsigned char) -1);\n+}\n+\n+/* vcvttsd2sis: source V2DF extracts scalar double (64-bit),\n+ Intel syntax needs \"qword ptr\" for memory operand. */\n+\n+int\n+test_vcvttsd2sis32 (__v2df *p)\n+{\n+ return (int) __builtin_ia32_cvttsd2sis32_round (*p, 4);\n+}\n+\n+unsigned int\n+test_vcvttsd2usis32 (__v2df *p)\n+{\n+ return (unsigned int) __builtin_ia32_cvttsd2usis32_round (*p, 4);\n+}\n+\n+/* vcvttss2sis: source V4SF extracts scalar float (32-bit),\n+ Intel syntax needs \"dword ptr\" for memory operand. */\n+\n+int\n+test_vcvttss2sis32 (__v4sf *p)\n+{\n+ return (int) __builtin_ia32_cvttss2sis32_round (*p, 4);\n+}\n+\n+unsigned int\n+test_vcvttss2usis32 (__v4sf *p)\n+{\n+ return (unsigned int) __builtin_ia32_cvttss2usis32_round (*p, 4);\n+}\n","prefixes":[]}