{"id":2221743,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221743/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260410082332.102522-1-weijie.gao@mediatek.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260410082332.102522-1-weijie.gao@mediatek.com>","date":"2026-04-10T08:23:32","name":"pinctrl: mediatek: mt7981: fix some register offsets and fields","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5c0b7bd011dbc3d39f30a84907b51a0415a4dc7f","submitter":{"id":75269,"url":"http://patchwork.ozlabs.org/api/1.1/people/75269/?format=json","name":"Weijie Gao","email":"weijie.gao@mediatek.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260410082332.102522-1-weijie.gao@mediatek.com/mbox/","series":[{"id":499423,"url":"http://patchwork.ozlabs.org/api/1.1/series/499423/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499423","date":"2026-04-10T08:23:32","name":"pinctrl: mediatek: mt7981: fix some register offsets and fields","version":1,"mbox":"http://patchwork.ozlabs.org/series/499423/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221743/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221743/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256\n header.s=dk header.b=RIk90PDJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n d=mediatek.com;\n s=dk;\n h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From;\n bh=+F1G5wV1KcjK0Fpp3uO+TleLgKG0yljmyHKiFjuvz88=;\n b=RIk90PDJpHDwFlcHqxKgCCi6y0Twhx/erVqTRdMq84Syth9mDeGXkZxvPaR1cvzZ6YuNXFbPSBzoNf79mg771X9lsMiFznf1tWY8S3k3VndR9uqdLVyAhp7AStHTedwkeQWjezhpQ3fJ/gyPen+Rb0nar7Mi5d5c7+S0L2fNsCk=;","X-CID-P-RULE":"Release_Ham","X-CID-O-INFO":"VERSION:1.3.12, REQID:288c257d-a60f-44fc-80f9-f65c2fed07d5,\n IP:0,\n U\n RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:\n release,TS:0","X-CID-META":"VersionHash:e7bac3a, CLOUDID:f980b524-cb5c-4236-a89a-9a7fb20c9bc4,\n B\n ulkID:nil,BulkQuantity:0,Recheck:0,SF:102|836|865|888|898,TC:-5,Content:0|\n 15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI:0\n ,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0","X-CID-BVR":"2,SSN|SDN","X-CID-BAS":"2,SSN|SDN,0,_","X-CID-FACTOR":"TF_CID_SPAM_SNR","X-CID-RHF":"D41D8CD98F00B204E9800998ECF8427E","From":"Weijie Gao ","To":"","CC":"GSS_MTK_Uboot_upstream , Tom Rini\n , Weijie Gao ","Subject":"[PATCH] pinctrl: mediatek: mt7981: fix some register offsets and\n fields","Date":"Fri, 10 Apr 2026 16:23:32 +0800","Message-ID":"<20260410082332.102522-1-weijie.gao@mediatek.com>","X-Mailer":"git-send-email 2.17.0","MIME-Version":"1.0","Content-Type":"text/plain","X-MTK":"N","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"This patch fixes mt7981 pin register offsets and field definitions.\n\nSigned-off-by: Weijie Gao \n---\n drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 ++++++++--------\n 1 file changed, 8 insertions(+), 8 deletions(-)","diff":"diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c\nindex 8875c276f36..5219b147797 100644\n--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c\n+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c\n@@ -106,7 +106,7 @@ static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {\n \n \tPIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),\n \tPIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),\n-\tPIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),\n+\tPIN_FIELD_BASE(11, 11, 5, 0x20, 0x10, 10, 1),\n \tPIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),\n \tPIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),\n \n@@ -215,7 +215,7 @@ static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {\n \tPIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),\n \tPIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),\n \tPIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),\n-\tPIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),\n+\tPIN_FIELD_BASE(44, 44, 7, 0x70, 0x10, 8, 1),\n \tPIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),\n \tPIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),\n \tPIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),\n@@ -279,8 +279,8 @@ static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {\n \n \tPIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),\n \n-\tPIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),\n-\tPIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),\n+\tPIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 3),\n+\tPIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 3),\n \tPIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),\n \tPIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),\n \tPIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),\n@@ -288,9 +288,9 @@ static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {\n \n \tPIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),\n \tPIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),\n-\tPIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),\n+\tPIN_FIELD_BASE(11, 11, 5, 0x10, 0x10, 0, 3),\n \tPIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),\n-\tPIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),\n+\tPIN_FIELD_BASE(13, 13, 5, 0x10, 0x10, 3, 3),\n \n \tPIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),\n \n@@ -302,7 +302,7 @@ static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {\n \tPIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),\n \tPIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),\n \tPIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),\n-\tPIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),\n+\tPIN_FIELD_BASE(23, 23, 2, 0x10, 0x10, 0, 3),\n \tPIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),\n \tPIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),\n \n@@ -368,7 +368,7 @@ static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {\n \tPIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),\n \tPIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),\n \tPIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),\n-\tPIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),\n+\tPIN_FIELD_BASE(20, 20, 2, 0x30, 0x10, 3, 1),\n \tPIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),\n \tPIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),\n \tPIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),\n","prefixes":[]}