{"id":2221600,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221600/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-6-lucaaamaral@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260409220614.65558-6-lucaaamaral@gmail.com>","date":"2026-04-09T22:06:13","name":"[v6,5/6] target/arm/emulate: add atomic, compare-and-swap, and PAC load","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a8b317d7e940f171f2e59fae200d36d88d0065f6","submitter":{"id":92822,"url":"http://patchwork.ozlabs.org/api/1.1/people/92822/?format=json","name":"Lucas Amaral","email":"lucaaamaral@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-6-lucaaamaral@gmail.com/mbox/","series":[{"id":499364,"url":"http://patchwork.ozlabs.org/api/1.1/series/499364/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499364","date":"2026-04-09T22:06:10","name":"target/arm: ISV=0 data abort emulation library","version":6,"mbox":"http://patchwork.ozlabs.org/series/499364/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221600/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221600/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=EpK1SovZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::132d;\n envelope-from=lucaaamaral@gmail.com; helo=mail-dy1-x132d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add emulation for remaining ISV=0 load/store instruction classes.\n\nAtomic memory operations (DDI 0487 C3.3.2):\n - LDADD, LDCLR, LDEOR, LDSET: arithmetic/logic atomics\n - LDSMAX, LDSMIN, LDUMAX, LDUMIN: signed/unsigned min/max\n - SWP: atomic swap\n Non-atomic read-modify-write, sufficient for MMIO where concurrent\n access is not a concern. Acquire/release semantics are ignored.\n\nCompare-and-swap (DDI 0487 C3.3.1):\n - CAS/CASA/CASAL/CASL: single-register compare-and-swap\n - CASP/CASPA/CASPAL/CASPL: register-pair compare-and-swap\n CASP validates even register pairs; odd or r31 returns UNHANDLED.\n\nLoad with PAC (DDI 0487 C6.2.121):\n - LDRAA/LDRAB: pointer-authenticated load, offset/pre-indexed\n Pointer authentication is not emulated (equivalent to auth always\n succeeding), which is correct for MMIO since PAC is a software\n security mechanism, not a memory access semantic.\n\nDecodetree differences from TCG:\n - %ldra_imm extracts the raw S:imm9 field; the handler scales by\n << 3. TCG applies !function=times_8 in the formatter.\n - @ldra uses wildcards for fixed opcode bits that TCG locks down\n (bits 31:30, bit 20, bit 11); the fixed bits are matched by the\n instruction pattern instead.\n - @cas is an explicit format template; TCG uses inline field\n extraction.\n\nCASP uses two explicit decode patterns for the 32/64-bit size\nvariants. LDRA's offset immediate is stored raw in the decode;\nthe handler scales by << 3.\n\nSigned-off-by: Lucas Amaral \n---\n target/arm/emulate/a64-ldst.decode | 45 ++++++\n target/arm/emulate/arm_emulate.c | 233 +++++++++++++++++++++++++++++\n 2 files changed, 278 insertions(+)","diff":"diff --git a/target/arm/emulate/a64-ldst.decode b/target/arm/emulate/a64-ldst.decode\nindex fadf6fd2..9292bfdf 100644\n--- a/target/arm/emulate/a64-ldst.decode\n+++ b/target/arm/emulate/a64-ldst.decode\n@@ -16,6 +16,16 @@\n # Load/store pair (GPR and SIMD/FP)\n &ldstpair rt2 rt rn imm sz sign w p\n \n+# Atomic memory operations\n+&atomic rs rn rt a r sz\n+\n+# Compare-and-swap\n+&cas rs rn rt sz a r\n+\n+# Load with PAC (LDRAA/LDRAB, FEAT_PAuth)\n+%ldra_imm 22:s1 12:9\n+&ldra rt rn imm m w\n+\n # Load/store register offset\n &ldst rm rn rt sign ext sz opt s\n \n@@ -36,6 +46,15 @@\n # Load/store pair: imm7 is signed, scaled by element size in handler\n @ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair\n \n+# Atomics\n+@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic\n+\n+# Compare-and-swap: sz extracted by pattern (CAS) or set constant (CASP)\n+@cas .. ...... . a:1 . rs:5 r:1 ..... rn:5 rt:5 &cas\n+\n+# Load with PAC\n+@ldra .. ... . .. m:1 . . ......... w:1 . rn:5 rt:5 &ldra imm=%ldra_imm\n+\n # Load/store register offset\n @ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst\n \n@@ -241,6 +260,32 @@ STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=\n LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0\n LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4\n \n+### Compare-and-swap\n+\n+# CAS / CASA / CASAL / CASL\n+CAS sz:2 001000 1 . 1 ..... . 11111 ..... ..... @cas\n+\n+# CASP / CASPA / CASPAL / CASPL (pair: Rt,Rt+1 and Rs,Rs+1)\n+CASP 00 001000 0 . 1 ..... . 11111 ..... ..... @cas sz=2\n+CASP 01 001000 0 . 1 ..... . 11111 ..... ..... @cas sz=3\n+\n+### Atomic memory operations\n+\n+LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic\n+LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic\n+LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic\n+LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic\n+LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic\n+LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic\n+LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic\n+LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic\n+SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic\n+\n+### Load with PAC (FEAT_PAuth)\n+\n+# LDRAA (M=0) / LDRAB (M=1), offset (W=0) / pre-indexed (W=1)\n+LDRA 11 111 0 00 . . 1 ......... . 1 ..... ..... @ldra\n+\n ### System instructions — DC cache maintenance\n \n # SYS with CRn=C7 covers all data cache operations (DC CIVAC, CVAC, etc.).\ndiff --git a/target/arm/emulate/arm_emulate.c b/target/arm/emulate/arm_emulate.c\nindex 7f876355..6601c9dc 100644\n--- a/target/arm/emulate/arm_emulate.c\n+++ b/target/arm/emulate/arm_emulate.c\n@@ -547,6 +547,239 @@ static bool trans_LDXP(DisasContext *ctx, arg_stxr *a)\n return true;\n }\n \n+/*\n+ * Atomic memory operations (DDI 0487 C3.3.2)\n+ *\n+ * Non-atomic read-modify-write; sufficient for MMIO.\n+ * Acquire/release semantics ignored (sequentially consistent by design).\n+ */\n+\n+typedef uint64_t (*atomic_op_fn)(uint64_t old, uint64_t operand, int bits);\n+\n+static uint64_t atomic_add(uint64_t old, uint64_t op, int bits)\n+{\n+ return old + op;\n+}\n+\n+static uint64_t atomic_clr(uint64_t old, uint64_t op, int bits)\n+{\n+ return old & ~op;\n+}\n+\n+static uint64_t atomic_eor(uint64_t old, uint64_t op, int bits)\n+{\n+ return old ^ op;\n+}\n+\n+static uint64_t atomic_set(uint64_t old, uint64_t op, int bits)\n+{\n+ return old | op;\n+}\n+\n+static uint64_t atomic_smax(uint64_t old, uint64_t op, int bits)\n+{\n+ int64_t a = sextract64(old, 0, bits);\n+ int64_t b = sextract64(op, 0, bits);\n+ return (a >= b) ? old : op;\n+}\n+\n+static uint64_t atomic_smin(uint64_t old, uint64_t op, int bits)\n+{\n+ int64_t a = sextract64(old, 0, bits);\n+ int64_t b = sextract64(op, 0, bits);\n+ return (a <= b) ? old : op;\n+}\n+\n+static uint64_t atomic_umax(uint64_t old, uint64_t op, int bits)\n+{\n+ uint64_t mask = (bits == 64) ? UINT64_MAX : (1ULL << bits) - 1;\n+ return ((old & mask) >= (op & mask)) ? old : op;\n+}\n+\n+static uint64_t atomic_umin(uint64_t old, uint64_t op, int bits)\n+{\n+ uint64_t mask = (bits == 64) ? UINT64_MAX : (1ULL << bits) - 1;\n+ return ((old & mask) <= (op & mask)) ? old : op;\n+}\n+\n+static bool do_atomic(DisasContext *ctx, arg_atomic *a, atomic_op_fn fn)\n+{\n+ int esize = 1 << a->sz;\n+ int bits = 8 * esize;\n+ uint64_t va = base_read(ctx, a->rn);\n+ uint8_t buf[8];\n+\n+ if (mem_read(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+\n+ uint64_t old = mem_ld(ctx, buf, esize);\n+ uint64_t operand = gpr_read(ctx, a->rs);\n+ uint64_t result = fn(old, operand, bits);\n+\n+ mem_st(ctx, buf, esize, result);\n+ if (mem_write(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+\n+ /* Rt receives the old value (before modification) */\n+ gpr_write(ctx, a->rt, old);\n+ return true;\n+}\n+\n+static bool trans_LDADD(DisasContext *ctx, arg_atomic *a)\n+{\n+ return do_atomic(ctx, a, atomic_add);\n+}\n+\n+static bool trans_LDCLR(DisasContext *ctx, arg_atomic *a)\n+{\n+ return do_atomic(ctx, a, atomic_clr);\n+}\n+\n+static bool trans_LDEOR(DisasContext *ctx, arg_atomic *a)\n+{\n+ return do_atomic(ctx, a, atomic_eor);\n+}\n+\n+static bool trans_LDSET(DisasContext *ctx, arg_atomic *a)\n+{\n+ return do_atomic(ctx, a, atomic_set);\n+}\n+\n+static bool trans_LDSMAX(DisasContext *ctx, arg_atomic *a)\n+{\n+ return do_atomic(ctx, a, atomic_smax);\n+}\n+\n+static bool trans_LDSMIN(DisasContext *ctx, arg_atomic *a)\n+{\n+ return do_atomic(ctx, a, atomic_smin);\n+}\n+\n+static bool trans_LDUMAX(DisasContext *ctx, arg_atomic *a)\n+{\n+ return do_atomic(ctx, a, atomic_umax);\n+}\n+\n+static bool trans_LDUMIN(DisasContext *ctx, arg_atomic *a)\n+{\n+ return do_atomic(ctx, a, atomic_umin);\n+}\n+\n+static bool trans_SWP(DisasContext *ctx, arg_atomic *a)\n+{\n+ int esize = 1 << a->sz;\n+ uint64_t va = base_read(ctx, a->rn);\n+ uint8_t buf[8];\n+\n+ if (mem_read(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+\n+ uint64_t old = mem_ld(ctx, buf, esize);\n+ mem_st(ctx, buf, esize, gpr_read(ctx, a->rs));\n+ if (mem_write(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+\n+ gpr_write(ctx, a->rt, old);\n+ return true;\n+}\n+\n+/* Compare-and-swap: CAS, CASP (DDI 0487 C3.3.1) */\n+\n+static bool trans_CAS(DisasContext *ctx, arg_cas *a)\n+{\n+ int esize = 1 << a->sz;\n+ uint64_t va = base_read(ctx, a->rn);\n+ uint8_t buf[8];\n+\n+ if (mem_read(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+\n+ uint64_t current = mem_ld(ctx, buf, esize);\n+ uint64_t mask = (esize == 8) ? UINT64_MAX : (1ULL << (8 * esize)) - 1;\n+ uint64_t compare = gpr_read(ctx, a->rs) & mask;\n+\n+ if ((current & mask) == compare) {\n+ uint64_t newval = gpr_read(ctx, a->rt) & mask;\n+ mem_st(ctx, buf, esize, newval);\n+ if (mem_write(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+ }\n+\n+ /* Rs receives the old memory value (whether or not swap occurred) */\n+ gpr_write(ctx, a->rs, current);\n+ return true;\n+}\n+\n+/* CASP: compare-and-swap pair (Rs,Rs+1 compared; Rt,Rt+1 stored) */\n+static bool trans_CASP(DisasContext *ctx, arg_cas *a)\n+{\n+ /* CASP requires even register pairs; odd or r31 is UNPREDICTABLE */\n+ if ((a->rs & 1) || a->rs >= 31 || (a->rt & 1) || a->rt >= 31) {\n+ return false;\n+ }\n+\n+ int esize = 1 << a->sz; /* per-register size */\n+ uint64_t va = base_read(ctx, a->rn);\n+ uint8_t buf[16];\n+\n+ if (mem_read(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+ uint64_t cur1 = mem_ld(ctx, buf, esize);\n+ uint64_t cur2 = mem_ld(ctx, buf + esize, esize);\n+\n+ uint64_t mask = (esize == 8) ? UINT64_MAX : (1ULL << (8 * esize)) - 1;\n+ uint64_t cmp1 = gpr_read(ctx, a->rs) & mask;\n+ uint64_t cmp2 = gpr_read(ctx, a->rs + 1) & mask;\n+\n+ if ((cur1 & mask) == cmp1 && (cur2 & mask) == cmp2) {\n+ uint64_t new1 = gpr_read(ctx, a->rt) & mask;\n+ uint64_t new2 = gpr_read(ctx, a->rt + 1) & mask;\n+ mem_st(ctx, buf, esize, new1);\n+ mem_st(ctx, buf + esize, esize, new2);\n+ if (mem_write(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+ }\n+\n+ gpr_write(ctx, a->rs, cur1);\n+ gpr_write(ctx, a->rs + 1, cur2);\n+ return true;\n+}\n+\n+/*\n+ * Load with PAC: LDRAA / LDRAB (FEAT_PAuth)\n+ * (DDI 0487 C6.2.121)\n+ *\n+ * Pointer authentication is not emulated -- the base register is used\n+ * directly (equivalent to auth always succeeding).\n+ */\n+\n+static bool trans_LDRA(DisasContext *ctx, arg_ldra *a)\n+{\n+ int64_t offset = (int64_t)a->imm << 3; /* S:imm9, scaled by 8 */\n+ uint64_t base = base_read(ctx, a->rn);\n+ uint64_t va = base + offset; /* auth not emulated */\n+ uint8_t buf[8];\n+\n+ if (mem_read(ctx, va, buf, 8) != 0) {\n+ return true;\n+ }\n+\n+ gpr_write(ctx, a->rt, mem_ld(ctx, buf, 8));\n+\n+ if (a->w) {\n+ base_write(ctx, a->rn, va);\n+ }\n+ return true;\n+}\n+\n /* PRFM, DC cache maintenance -- treated as NOP */\n static bool trans_NOP(DisasContext *ctx, arg_NOP *a)\n {\n","prefixes":["v6","5/6"]}