{"id":2221598,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221598/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-5-lucaaamaral@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260409220614.65558-5-lucaaamaral@gmail.com>","date":"2026-04-09T22:06:12","name":"[v6,4/6] target/arm/emulate: add load/store exclusive","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"739dde2ce5950b102c615fcf91d7ae4cafd60aa7","submitter":{"id":92822,"url":"http://patchwork.ozlabs.org/api/1.1/people/92822/?format=json","name":"Lucas Amaral","email":"lucaaamaral@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-5-lucaaamaral@gmail.com/mbox/","series":[{"id":499364,"url":"http://patchwork.ozlabs.org/api/1.1/series/499364/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499364","date":"2026-04-09T22:06:10","name":"target/arm: ISV=0 data abort emulation library","version":6,"mbox":"http://patchwork.ozlabs.org/series/499364/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221598/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221598/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=EJqH9Or3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::1329;\n envelope-from=lucaaamaral@gmail.com; helo=mail-dy1-x1329.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add emulation for load/store exclusive instructions (DDI 0487 C3.3.6).\nExclusive monitors have no meaning on emulated MMIO accesses, so STXR\nalways reports success (Rs=0) and LDXR does not set a monitor.\n\nInstruction coverage:\n - STXR/STLXR: exclusive store, 8/16/32/64-bit\n - LDXR/LDAXR: exclusive load, 8/16/32/64-bit\n - STXP/STLXP: exclusive store pair, 32/64-bit\n - LDXP/LDAXP: exclusive load pair, 32/64-bit\n\nSTXP/LDXP use two explicit decode patterns (sz=2, sz=3) for the\n32/64-bit size variants.\n\nSigned-off-by: Lucas Amaral \n---\n target/arm/emulate/a64-ldst.decode | 22 ++++++++++\n target/arm/emulate/arm_emulate.c | 70 ++++++++++++++++++++++++++++++\n 2 files changed, 92 insertions(+)","diff":"diff --git a/target/arm/emulate/a64-ldst.decode b/target/arm/emulate/a64-ldst.decode\nindex f3de3f86..fadf6fd2 100644\n--- a/target/arm/emulate/a64-ldst.decode\n+++ b/target/arm/emulate/a64-ldst.decode\n@@ -10,6 +10,9 @@\n # 'u' flag: 0 = 9-bit signed immediate (byte offset), 1 = 12-bit unsigned (needs << sz)\n &ldst_imm rt rn imm sz sign w p unpriv ext u\n \n+# Load/store exclusive\n+&stxr rn rt rt2 rs sz lasr\n+\n # Load/store pair (GPR and SIMD/FP)\n &ldstpair rt2 rt rn imm sz sign w p\n \n@@ -18,6 +21,9 @@\n \n ### Format templates\n \n+# Exclusives\n+@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr\n+\n # Load/store immediate (9-bit signed)\n @ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm u=0 unpriv=0 p=0 w=0\n @ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm u=0 unpriv=0 p=0 w=1\n@@ -134,6 +140,22 @@ STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=\n LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0\n LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4\n \n+### Load/store exclusive\n+\n+# STXR / STLXR (sz encodes 8/16/32/64-bit)\n+STXR .. 001000 000 ..... . ..... ..... ..... @stxr\n+\n+# LDXR / LDAXR\n+LDXR .. 001000 010 ..... . ..... ..... ..... @stxr\n+\n+# STXP / STLXP (bit[31]=1, bit[30]=sf → sz=2 for 32-bit, sz=3 for 64-bit)\n+STXP 10 001000 001 rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=2\n+STXP 11 001000 001 rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=3\n+\n+# LDXP / LDAXP\n+LDXP 10 001000 011 rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=2\n+LDXP 11 001000 011 rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=3\n+\n ### Load/store pair — non-temporal (STNP/LDNP)\n \n # STNP/LDNP: offset only, no writeback. Non-temporal hint ignored.\ndiff --git a/target/arm/emulate/arm_emulate.c b/target/arm/emulate/arm_emulate.c\nindex 2d86b90f..7f876355 100644\n--- a/target/arm/emulate/arm_emulate.c\n+++ b/target/arm/emulate/arm_emulate.c\n@@ -477,6 +477,76 @@ static bool trans_LDR_v(DisasContext *ctx, arg_ldst *a)\n return true;\n }\n \n+/*\n+ * Load/store exclusive: STXR, LDXR, STXP, LDXP\n+ * (DDI 0487 C3.3.6)\n+ *\n+ * Exclusive monitors have no meaning on MMIO. STXR always reports\n+ * success (Rs=0) and LDXR does not set an exclusive monitor.\n+ */\n+\n+static bool trans_STXR(DisasContext *ctx, arg_stxr *a)\n+{\n+ int esize = 1 << a->sz;\n+ uint64_t va = base_read(ctx, a->rn);\n+ uint8_t buf[8];\n+\n+ mem_st(ctx, buf, esize, gpr_read(ctx, a->rt));\n+ if (mem_write(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+\n+ /* Report success -- no exclusive monitor on emulated access */\n+ gpr_write(ctx, a->rs, 0);\n+ return true;\n+}\n+\n+static bool trans_LDXR(DisasContext *ctx, arg_stxr *a)\n+{\n+ int esize = 1 << a->sz;\n+ uint64_t va = base_read(ctx, a->rn);\n+ uint8_t buf[8];\n+\n+ if (mem_read(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+\n+ gpr_write(ctx, a->rt, mem_ld(ctx, buf, esize));\n+ return true;\n+}\n+\n+static bool trans_STXP(DisasContext *ctx, arg_stxr *a)\n+{\n+ int esize = 1 << a->sz; /* sz=2->4, sz=3->8 */\n+ uint64_t va = base_read(ctx, a->rn);\n+ uint8_t buf[16];\n+\n+ mem_st(ctx, buf, esize, gpr_read(ctx, a->rt));\n+ mem_st(ctx, buf + esize, esize, gpr_read(ctx, a->rt2));\n+\n+ if (mem_write(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+\n+ gpr_write(ctx, a->rs, 0); /* success */\n+ return true;\n+}\n+\n+static bool trans_LDXP(DisasContext *ctx, arg_stxr *a)\n+{\n+ int esize = 1 << a->sz;\n+ uint64_t va = base_read(ctx, a->rn);\n+ uint8_t buf[16];\n+\n+ if (mem_read(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+\n+ gpr_write(ctx, a->rt, mem_ld(ctx, buf, esize));\n+ gpr_write(ctx, a->rt2, mem_ld(ctx, buf + esize, esize));\n+ return true;\n+}\n+\n /* PRFM, DC cache maintenance -- treated as NOP */\n static bool trans_NOP(DisasContext *ctx, arg_NOP *a)\n {\n","prefixes":["v6","4/6"]}