{"id":2221597,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221597/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-4-lucaaamaral@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260409220614.65558-4-lucaaamaral@gmail.com>","date":"2026-04-09T22:06:11","name":"[v6,3/6] target/arm/emulate: add load/store pair","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ebacff1e5fe6aa2b3a0167ccebb16b23f371339a","submitter":{"id":92822,"url":"http://patchwork.ozlabs.org/api/1.1/people/92822/?format=json","name":"Lucas Amaral","email":"lucaaamaral@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-4-lucaaamaral@gmail.com/mbox/","series":[{"id":499364,"url":"http://patchwork.ozlabs.org/api/1.1/series/499364/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499364","date":"2026-04-09T22:06:10","name":"target/arm: ISV=0 data abort emulation library","version":6,"mbox":"http://patchwork.ozlabs.org/series/499364/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221597/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221597/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Ox19hzQ6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsDZP1ScSz1yCv\n\tfor ; Fri, 10 Apr 2026 08:07:41 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wAxWJ-00089l-Hz; Thu, 09 Apr 2026 18:06:39 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wAxWH-00088p-UB\n for qemu-devel@nongnu.org; Thu, 09 Apr 2026 18:06:37 -0400","from mail-dy1-x1334.google.com ([2607:f8b0:4864:20::1334])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wAxWF-0000bj-Nu\n for qemu-devel@nongnu.org; Thu, 09 Apr 2026 18:06:37 -0400","by mail-dy1-x1334.google.com with SMTP id\n 5a478bee46e88-2c54c68db4dso2370619eec.0\n for ; Thu, 09 Apr 2026 15:06:35 -0700 (PDT)","from localhost.localdomain ([2804:7f4:c030:bb40:195d:78fd:ecba:d45])\n by smtp.gmail.com with ESMTPSA id\n 5a478bee46e88-2d561bde68bsm1534567eec.17.2026.04.09.15.06.29\n (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256);\n Thu, 09 Apr 2026 15:06:33 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1775772394; x=1776377194; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=9hYjt5TP5fiILetOflamrBDH1HToT8NoGi40uxHb3Qw=;\n b=Ox19hzQ6s0TCJJohcsgjIjPdiHFgZl9O0iQ1GTLCTwTjdcqgHdAxGeiIqBbwJhln4v\n qZ1tkExiIJL27D0WrTIL/rCM+SmL+VDgbMQOMTdfEEf8Q4WlYw6+66HF1yte4LEDRsi7\n eqrcGYvCKQFn7jyf21PNvMASFgKYb+CnYGsKyaD5K+l3Lx2XxXi2b7Jk8xQjvIC4SPG2\n u1tg9u+Z0ECGrn1/UpErPTDQW/3rmW7hywntDrV6xS6atJSxqqfzp1XbQcr6KZMIhtES\n ZcYZmD4GKT7BC5Iw9YxJkJDEy9K6+ioni2Fiojxj+l1PAsUviLaR1YMnHSl3hiAhhBbR\n pxug==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775772394; x=1776377194;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=9hYjt5TP5fiILetOflamrBDH1HToT8NoGi40uxHb3Qw=;\n b=owqPE4+dlzDWqHphqfymQPVHV1b+PE9/b1nhzQ/nR2rJBXy+ByuNpR/WQ4ehb73q+j\n ipooU2TG2Wwh8Dj4dpcGeHcQ4rys9LQhJOlYMXvZoZ9mEkfoA+Ef3rSZh9zcuiEhvlu1\n 44gtJxxR/kzAo7WgX31Nl90R/XB8X54wcrBPEBNha5tDd6SeSPriWMS3B65WBga8i5A6\n pMph2JXt1sB1X8XSjZM7J2GsMRiO8dI10jf0u++4MJxSOYwe8e7KWyV+BavhHfXcuZvR\n R5M65vXR33YKtqAtmhnZRMs0X2RtporWPeP2R+ytTDh6LoJZU9bDqrwn6M7vC5/CRSvk\n MOpg==","X-Gm-Message-State":"AOJu0YxcWZgySBzqCxsBrkzGBPnQ1e/z+zi9j6T9AWKLEF7aqqK/NgNE\n GI1sfVSCHOg3Rqt7Icul+q2HTP3o8AtFkfoFsBinAKxAiZQTGBR7EMLG3VK1b+8V","X-Gm-Gg":"AeBDies4pVxfUZ2WvAb0+JS8eervdvk+MPExEdMr4icph+rjb2LLgRUpzWa64MyB7Nn\n vkypaZaAXHdBjYz06Z0I2r/l8m79cfF/8Kx8dxr7Y52tEJcYjoFOpNwnwI/jQu6wrlDt15KA24N\n GbW8Txs7s/mcqbaF8sIS+800957JM8iY89pkDklMisEI3/Ajgoh2elSjOARR5ntG/E7qLod4a7b\n zxy9Y/sUMEGwfSEw4vX/qpXokK7qFQGE8k5GmXjAsmjI6sBQDASU9Clah3pRHdnJdsXl9mpx9YT\n tGNb07gwH3yyuDeZAkQglUN9XcWOhGyLcYmOGL7DTB3PbTHE2sRtkkul5F/QPR5eTX1/DZSR7na\n MeJPXAjl5kBz7Dd4tLj/v9vTvS/7IHTjLrYCtF9duQH0E64JerfZeSTg9E6OZs/4R9NlRnXZs+R\n t0qWeBPx0rJ6IJaXk03t3QcgJ/PSKuuOH0MSgeSUvrAIC/Yf8GrwxYphogOhuymIOwfdhmjoX0","X-Received":"by 2002:a05:7300:6da8:b0:2c4:a862:2368 with SMTP id\n 5a478bee46e88-2d5871bcb93mr529162eec.2.1775772393713;\n Thu, 09 Apr 2026 15:06:33 -0700 (PDT)","From":"Lucas Amaral ","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org, agraf@csgraf.de, peter.maydell@linaro.org,\n mohamed@unpredictable.fr, alex.bennee@linaro.org,\n richard.henderson@linaro.org, Lucas Amaral ","Subject":"[PATCH v6 3/6] target/arm/emulate: add load/store pair","Date":"Thu, 9 Apr 2026 19:06:11 -0300","Message-ID":"<20260409220614.65558-4-lucaaamaral@gmail.com>","X-Mailer":"git-send-email 2.52.0","In-Reply-To":"<20260409220614.65558-1-lucaaamaral@gmail.com>","References":"<20260409220614.65558-1-lucaaamaral@gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::1334;\n envelope-from=lucaaamaral@gmail.com; helo=mail-dy1-x1334.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add emulation for load/store pair instructions (DDI 0487 C3.3.14 --\nC3.3.16). All addressing modes are covered: non-temporal (STNP/LDNP),\npost-indexed, signed offset, and pre-indexed.\n\nInstruction coverage:\n - STP/LDP (GPR): 32/64-bit pairs, all addressing modes\n - STP/LDP (SIMD/FP): 32/64/128-bit pairs, all addressing modes\n - LDPSW: sign-extending 32-bit pair load\n - STGP: store allocation tag pair (tag operation is NOP for MMIO)\n\nSigned-off-by: Lucas Amaral \n---\n target/arm/emulate/a64-ldst.decode | 68 ++++++++++++++++++\n target/arm/emulate/arm_emulate.c | 108 +++++++++++++++++++++++++++++\n 2 files changed, 176 insertions(+)","diff":"diff --git a/target/arm/emulate/a64-ldst.decode b/target/arm/emulate/a64-ldst.decode\nindex af6babe1..f3de3f86 100644\n--- a/target/arm/emulate/a64-ldst.decode\n+++ b/target/arm/emulate/a64-ldst.decode\n@@ -10,6 +10,9 @@\n # 'u' flag: 0 = 9-bit signed immediate (byte offset), 1 = 12-bit unsigned (needs << sz)\n &ldst_imm rt rn imm sz sign w p unpriv ext u\n \n+# Load/store pair (GPR and SIMD/FP)\n+&ldstpair rt2 rt rn imm sz sign w p\n+\n # Load/store register offset\n &ldst rm rn rt sign ext sz opt s\n \n@@ -24,6 +27,9 @@\n # Load/store unsigned offset (12-bit, handler scales by << sz)\n @ldst_uimm .. ... . .. .. imm:12 rn:5 rt:5 &ldst_imm u=1 unpriv=0 p=0 w=0\n \n+# Load/store pair: imm7 is signed, scaled by element size in handler\n+@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair\n+\n # Load/store register offset\n @ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst\n \n@@ -128,6 +134,68 @@ STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=\n LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0\n LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4\n \n+### Load/store pair — non-temporal (STNP/LDNP)\n+\n+# STNP/LDNP: offset only, no writeback. Non-temporal hint ignored.\n+STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0\n+LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0\n+\n+### Load/store pair — post-indexed\n+\n+STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1\n+LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1\n+LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1\n+STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1\n+LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1\n+STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1\n+LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1\n+\n+### Load/store pair — signed offset\n+\n+STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0\n+STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0\n+LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0\n+\n+### Load/store pair — pre-indexed\n+\n+STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1\n+LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1\n+LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1\n+STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1\n+LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1\n+STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1\n+LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1\n+\n+### Load/store pair — STGP (store allocation tag + pair)\n+\n+STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+\n ### Load/store register — register offset\n \n # GPR\ndiff --git a/target/arm/emulate/arm_emulate.c b/target/arm/emulate/arm_emulate.c\nindex 79f42d44..2d86b90f 100644\n--- a/target/arm/emulate/arm_emulate.c\n+++ b/target/arm/emulate/arm_emulate.c\n@@ -171,6 +171,114 @@ static uint64_t load_extend(uint64_t val, int sz, int sign, int ext)\n return val;\n }\n \n+/*\n+ * Load/store pair: STP, LDP, STNP, LDNP, STGP, LDPSW\n+ * (DDI 0487 C3.3.14 -- C3.3.16)\n+ */\n+\n+static bool trans_STP(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ int esize = 1 << a->sz; /* 4 or 8 bytes */\n+ int64_t offset = (int64_t)a->imm << a->sz;\n+ uint64_t base = base_read(ctx, a->rn);\n+ uint64_t va = a->p ? base : base + offset; /* post-index: unmodified base */\n+ uint8_t buf[16]; /* max 2 x 8 bytes */\n+\n+ mem_st(ctx, buf, esize, gpr_read(ctx, a->rt));\n+ mem_st(ctx, buf + esize, esize, gpr_read(ctx, a->rt2));\n+\n+ if (mem_write(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+\n+ if (a->w) {\n+ base_write(ctx, a->rn, base + offset);\n+ }\n+ return true;\n+}\n+\n+static bool trans_LDP(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ int esize = 1 << a->sz;\n+ int64_t offset = (int64_t)a->imm << a->sz;\n+ uint64_t base = base_read(ctx, a->rn);\n+ uint64_t va = a->p ? base : base + offset;\n+ uint8_t buf[16];\n+\n+ if (mem_read(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+ uint64_t v1 = mem_ld(ctx, buf, esize);\n+ uint64_t v2 = mem_ld(ctx, buf + esize, esize);\n+\n+ /* LDPSW: sign-extend 32-bit values to 64-bit (sign=1, sz=2) */\n+ if (a->sign) {\n+ v1 = sextract64(v1, 0, 8 * esize);\n+ v2 = sextract64(v2, 0, 8 * esize);\n+ }\n+\n+ gpr_write(ctx, a->rt, v1);\n+ gpr_write(ctx, a->rt2, v2);\n+\n+ if (a->w) {\n+ base_write(ctx, a->rn, base + offset);\n+ }\n+ return true;\n+}\n+\n+/* STGP: tag operation is a NOP for emulation; data stored via STP */\n+static bool trans_STGP(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ return trans_STP(ctx, a);\n+}\n+\n+/*\n+ * SIMD/FP load/store pair: STP_v, LDP_v\n+ * (DDI 0487 C3.3.14 -- C3.3.16)\n+ */\n+\n+static bool trans_STP_v(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ int esize = 1 << a->sz; /* 4, 8, or 16 bytes */\n+ int64_t offset = (int64_t)a->imm << a->sz;\n+ uint64_t base = base_read(ctx, a->rn);\n+ uint64_t va = a->p ? base : base + offset;\n+ uint8_t buf[32]; /* max 2 x 16 bytes */\n+\n+ fpreg_read(ctx, a->rt, buf, esize);\n+ fpreg_read(ctx, a->rt2, buf + esize, esize);\n+\n+ if (mem_write(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+\n+ if (a->w) {\n+ base_write(ctx, a->rn, base + offset);\n+ }\n+ return true;\n+}\n+\n+static bool trans_LDP_v(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ int esize = 1 << a->sz;\n+ int64_t offset = (int64_t)a->imm << a->sz;\n+ uint64_t base = base_read(ctx, a->rn);\n+ uint64_t va = a->p ? base : base + offset;\n+ uint8_t buf[32];\n+\n+ if (mem_read(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+\n+ fpreg_write(ctx, a->rt, buf, esize);\n+ fpreg_write(ctx, a->rt2, buf + esize, esize);\n+\n+ if (a->w) {\n+ base_write(ctx, a->rn, base + offset);\n+ }\n+ return true;\n+}\n+\n /* Load/store single -- immediate (GPR) (DDI 0487 C3.3.8 -- C3.3.13) */\n \n static bool trans_STR_i(DisasContext *ctx, arg_ldst_imm *a)\n","prefixes":["v6","3/6"]}