{"id":2221538,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221538/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409155344.2849233-2-bruno.vilaca.sa@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260409155344.2849233-2-bruno.vilaca.sa@gmail.com>","date":"2026-04-09T15:53:42","name":"[1/2] target/riscv: preserve RV32 henvcfgh on henvcfg writes","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b7ab9ecb9287179db25e7d2137254880e850daf0","submitter":{"id":93104,"url":"http://patchwork.ozlabs.org/api/1.1/people/93104/?format=json","name":"Bruno Sa","email":"bruno.vilaca.sa@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409155344.2849233-2-bruno.vilaca.sa@gmail.com/mbox/","series":[{"id":499332,"url":"http://patchwork.ozlabs.org/api/1.1/series/499332/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499332","date":"2026-04-09T15:53:42","name":"target/riscv: fix RV32 henvcfg/stateen CSR handling","version":1,"mbox":"http://patchwork.ozlabs.org/series/499332/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221538/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221538/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=KbvZJwFO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fs6Lb4L4Pz1yJK\n\tfor ; Fri, 10 Apr 2026 03:27:01 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wAt9C-0008R9-PQ; Thu, 09 Apr 2026 13:26:30 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wArho-0000Ob-6v\n for qemu-devel@nongnu.org; Thu, 09 Apr 2026 11:54:08 -0400","from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wArhm-0001Zh-R0\n for qemu-devel@nongnu.org; Thu, 09 Apr 2026 11:54:07 -0400","by mail-wr1-x42a.google.com with SMTP id\n ffacd0b85a97d-43cf73bbfbdso660560f8f.1\n for ; Thu, 09 Apr 2026 08:54:06 -0700 (PDT)","from ninolomata-AERO-15-KC.. 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A write to\nhenvcfg should therefore only update the low 32 bits of env->henvcfg.\n\nThe current write_henvcfg() path overwrites env->henvcfg with the\nlow-half value and clears any bits previously written via henvcfgh.\n\nPreserve the upper 32 bits on RV32 henvcfg writes and keep the existing\nRV64 behaviour unchanged.\n\nSigned-off-by: Bruno Sa \n---\n target/riscv/csr.c | 10 +++++++++-\n 1 file changed, 9 insertions(+), 1 deletion(-)","diff":"diff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex 7948188356..d322bdbd47 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -3326,7 +3326,15 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,\n }\n }\n \n- env->henvcfg = val & mask;\n+ if (riscv_cpu_mxl(env) == MXL_RV32) {\n+ /*\n+ * RV32 stores STCE/ADUE/PBMTE/DTE in henvcfgh, so a low-half henvcfg\n+ * write must not clobber the upper 32 bits.\n+ */\n+ env->henvcfg = (env->henvcfg & ~0xFFFFFFFFULL) | (val & mask);\n+ } else {\n+ env->henvcfg = val & mask;\n+ }\n if ((env->henvcfg & HENVCFG_DTE) == 0) {\n env->vsstatus &= ~MSTATUS_SDT;\n }\n","prefixes":["1/2"]}