{"id":2221535,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221535/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260409163736.2419396-1-prabhakar.mahadev-lad.rj@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260409163736.2419396-1-prabhakar.mahadev-lad.rj@bp.renesas.com>","date":"2026-04-09T16:37:36","name":"pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"aece7d9302e90777811e1f60f8cf76eba88cc0b4","submitter":{"id":9539,"url":"http://patchwork.ozlabs.org/api/1.1/people/9539/?format=json","name":"Lad, Prabhakar","email":"prabhakar.csengg@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260409163736.2419396-1-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/","series":[{"id":499329,"url":"http://patchwork.ozlabs.org/api/1.1/series/499329/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499329","date":"2026-04-09T16:37:36","name":"pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume","version":1,"mbox":"http://patchwork.ozlabs.org/series/499329/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221535/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221535/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=UppKiqZX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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i < 2; i++) {\n \t\tu32 n_dedicated_pins = pctrl->data->n_dedicated_pins;\n \n@@ -3002,7 +3008,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \tstruct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;\n \n \tfor (u32 port = 0; port < nports; port++) {\n-\t\tbool has_iolh, has_ien, has_pupd, has_smt;\n+\t\tbool has_iolh, has_ien, has_pupd, has_smt, has_sr;\n \t\tu32 off, caps;\n \t\tu8 pincnt;\n \t\tu64 cfg;\n@@ -3023,6 +3029,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \t\thas_ien = !!(caps & PIN_CFG_IEN);\n \t\thas_pupd = !!(caps & PIN_CFG_PUPD);\n \t\thas_smt = !!(caps & PIN_CFG_SMT);\n+\t\thas_sr = !!(caps & PIN_CFG_SR);\n \n \t\tif (suspend)\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);\n@@ -3068,6 +3075,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \n \t\tif (has_smt)\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]);\n+\n+\t\tif (has_sr)\n+\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), cache->sr[port]);\n \t}\n }\n \n","prefixes":[]}