{"id":2221197,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221197/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408140635.42546-2-zhiwei_liu@linux.alibaba.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408140635.42546-2-zhiwei_liu@linux.alibaba.com>","date":"2026-04-08T14:06:30","name":"[v5,1/6] target/riscv: Add basic definitions and CSRs for SMMPT","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b7767903c51fe41d8d218b4a004eddc6cce50dd1","submitter":{"id":84720,"url":"http://patchwork.ozlabs.org/api/1.1/people/84720/?format=json","name":"LIU Zhiwei","email":"zhiwei_liu@linux.alibaba.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408140635.42546-2-zhiwei_liu@linux.alibaba.com/mbox/","series":[{"id":499183,"url":"http://patchwork.ozlabs.org/api/1.1/series/499183/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499183","date":"2026-04-08T14:06:34","name":"target/riscv: Implement Smsdid and Smmpt extension","version":5,"mbox":"http://patchwork.ozlabs.org/series/499183/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221197/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221197/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default 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TI=SMTPD_---0X0f7V58_1775657233;","From":"LIU Zhiwei ","To":"qemu-devel@nongnu.org","Cc":"qemu-riscv@nongnu.org, chao.liu.zevorn@gmail.com, palmer@dabbelt.com,\n alistair23@gmail.com, daniel.barboza@oss.qualcomm.com, liwei1518@gmail.com,\n LIU Zhiwei ,\n Huang Tao ,\n TANG Tiancheng ,\n Daniel Henrique Barboza ","Subject":"[PATCH v5 1/6] target/riscv: Add basic definitions and CSRs for SMMPT","Date":"Wed, 8 Apr 2026 22:06:30 +0800","Message-Id":"<20260408140635.42546-2-zhiwei_liu@linux.alibaba.com>","X-Mailer":"git-send-email 2.39.3 (Apple Git-146)","In-Reply-To":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>","References":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=115.124.30.112;\n envelope-from=zhiwei_liu@linux.alibaba.com;\n helo=out30-112.freemail.mail.aliyun.com","X-Spam_score_int":"-174","X-Spam_score":"-17.5","X-Spam_bar":"-----------------","X-Spam_report":"(-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5,\n USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This patch lays the groundwork for the SMMPT (Supervisor Domains Access\nProtection) extension by introducing its fundamental components.\n\nIt adds:\n- New CPU configuration flags, `ext_smmpt` and `ext_smsdid`, to enable\n the extension.\n- Bit-field definitions for the `mmpt` CSR in `cpu_bits.h`.\n- The `mmpt` and `msdcfg` CSR numbers and their read/write handlers in\n `csr.c`.\n- New fields in `CPUArchState` to store the state of these new CSRs.\n- A new translation failure reason `TRANSLATE_MPT_FAIL`.\n\nThis provides the necessary infrastructure for the core MPT logic and\nMMU integration that will follow.\n\nCo-authored-by: Huang Tao \nCo-authored-by: TANG Tiancheng \nSigned-off-by: LIU Zhiwei \nReviewed-by: Daniel Henrique Barboza \n---\n target/riscv/cpu.h | 9 ++-\n target/riscv/cpu_bits.h | 27 +++++++++\n target/riscv/cpu_cfg_fields.h.inc | 2 +\n target/riscv/csr.c | 95 +++++++++++++++++++++++++++++++\n target/riscv/riscv_smmpt.h | 21 +++++++\n 5 files changed, 153 insertions(+), 1 deletion(-)\n create mode 100644 target/riscv/riscv_smmpt.h","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 35d1f6362c..f8265c2cc2 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -130,7 +130,8 @@ enum {\n TRANSLATE_SUCCESS,\n TRANSLATE_FAIL,\n TRANSLATE_PMP_FAIL,\n- TRANSLATE_G_STAGE_FAIL\n+ TRANSLATE_G_STAGE_FAIL,\n+ TRANSLATE_MPT_FAIL\n };\n \n /* Extension context status */\n@@ -181,6 +182,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[];\n #if !defined(CONFIG_USER_ONLY)\n #include \"pmp.h\"\n #include \"debug.h\"\n+#include \"riscv_smmpt.h\"\n #endif\n \n #define RV_VLEN_MAX 1024\n@@ -481,6 +483,11 @@ struct CPUArchState {\n uint64_t hstateen[SMSTATEEN_MAX_COUNT];\n uint64_t sstateen[SMSTATEEN_MAX_COUNT];\n uint64_t henvcfg;\n+ /* Smsdid */\n+ uint32_t mptmode;\n+ uint32_t sdid;\n+ uint64_t mptppn;\n+ uint32_t msdcfg;\n #endif\n \n /* Fields from here on are preserved across CPU reset. */\ndiff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h\nindex b62dd82fe7..c6a34863d1 100644\n--- a/target/riscv/cpu_bits.h\n+++ b/target/riscv/cpu_bits.h\n@@ -1164,4 +1164,31 @@ typedef enum CTRType {\n #define MCONTEXT64 0x0000000000001FFFULL\n #define MCONTEXT32_HCONTEXT 0x0000007F\n #define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL\n+\n+/* Smsdid */\n+#define CSR_MMPT 0xbc0\n+#define CSR_MSDCFG 0xbd1\n+\n+#define MMPT_MODE_MASK_32 0xC0000000\n+#define MMPT_SDID_MASK_32 0x3F000000\n+#define MMPT_PPN_MASK_32 0x003FFFFF\n+\n+#define MMPT_MODE_SHIFT_32 30\n+#define MMPT_SDID_SHIFT_32 24\n+\n+#define MMPT_MODE_MASK_64 0xF000000000000000ULL\n+#define MMPT_SDID_MASK_64 0x0FC0000000000000ULL\n+#define MMPT_PPN_MASK_64 0x000FFFFFFFFFFFFFULL\n+\n+#define MPTE_L3_VALID 0x0000100000000000ULL\n+#define MPTE_L3_RESERVED 0xFFFFE00000000000ULL\n+\n+#define MPTE_L2_RESERVED_64 0xFFFF800000000000ULL\n+#define MPTE_L2_RESERVED_32 0xFE000000\n+\n+#define MPTE_L1_RESERVED_64 0xFFFFFFFF00000000ULL\n+#define MPTE_L1_RESERVED_32 0xFFFF0000\n+\n+#define MMPT_MODE_SHIFT_64 60\n+#define MMPT_SDID_SHIFT_64 54\n #endif\ndiff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\nindex cd1a5ec56b..80644948dd 100644\n--- a/target/riscv/cpu_cfg_fields.h.inc\n+++ b/target/riscv/cpu_cfg_fields.h.inc\n@@ -63,6 +63,8 @@ BOOL_FIELD(ext_smpmpmt)\n BOOL_FIELD(ext_svrsw60t59b)\n BOOL_FIELD(ext_svvptc)\n BOOL_FIELD(ext_svukte)\n+BOOL_FIELD(ext_smmpt)\n+BOOL_FIELD(ext_smsdid)\n BOOL_FIELD(ext_zdinx)\n BOOL_FIELD(ext_zaamo)\n BOOL_FIELD(ext_zacas)\ndiff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex a75281539b..081d2fc2c3 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -793,6 +793,15 @@ static RISCVException rnmi(CPURISCVState *env, int csrno)\n \n return RISCV_EXCP_ILLEGAL_INST;\n }\n+\n+static RISCVException smsdid(CPURISCVState *env, int csrno)\n+{\n+ if (riscv_cpu_cfg(env)->ext_smsdid) {\n+ return RISCV_EXCP_NONE;\n+ }\n+\n+ return RISCV_EXCP_ILLEGAL_INST;\n+}\n #endif\n \n static RISCVException seed(CPURISCVState *env, int csrno)\n@@ -5446,6 +5455,89 @@ static RISCVException write_mnstatus(CPURISCVState *env, int csrno,\n return RISCV_EXCP_NONE;\n }\n \n+static RISCVException read_mmpt(CPURISCVState *env, int csrno,\n+ target_ulong *val)\n+{\n+ if (riscv_cpu_xlen(env) == 32) {\n+ uint32_t value = 0;\n+ value |= env->mptmode << MMPT_MODE_SHIFT_32;\n+ value |= (env->sdid << MMPT_SDID_SHIFT_32) & MMPT_SDID_MASK_32;\n+ value |= env->mptppn & MMPT_PPN_MASK_32;\n+ *val = value;\n+ } else if (riscv_cpu_xlen(env) == 64) {\n+ uint64_t value_64 = 0;\n+ uint32_t mode_value = env->mptmode;\n+ /* mpt_mode_t convert to mmpt.mode value */\n+ if (mode_value) {\n+ mode_value -= SMMPT43 - SMMPT34;\n+ }\n+ value_64 |= (uint64_t)mode_value << MMPT_MODE_SHIFT_64;\n+ value_64 |= ((uint64_t)env->sdid << MMPT_SDID_SHIFT_64)\n+ & MMPT_SDID_MASK_64;\n+ value_64 |= (uint64_t)env->mptppn & MMPT_PPN_MASK_64;\n+ *val = value_64;\n+ } else {\n+ return RISCV_EXCP_ILLEGAL_INST;\n+ }\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static RISCVException write_mmpt(CPURISCVState *env, int csrno,\n+ target_ulong val, uintptr_t ra)\n+{\n+ uint32_t mode_value = 0;\n+ if (!riscv_cpu_cfg(env)->ext_smmpt) {\n+ goto set_remaining_fields_zero;\n+ }\n+\n+ if (riscv_cpu_xlen(env) == 32) {\n+ mode_value = (val & MMPT_MODE_MASK_32) >> MMPT_MODE_SHIFT_32;\n+ /* If mode is bare, the remaining fields in mmpt must be zero */\n+ if (mode_value == SMMPTBARE) {\n+ goto set_remaining_fields_zero;\n+ } else if (mode_value <= SMMPT34) {\n+ /* Only write the legal value */\n+ env->mptmode = mode_value;\n+ }\n+ env->sdid = (val & MMPT_SDID_MASK_32) >> MMPT_SDID_SHIFT_32;\n+ env->mptppn = val & MMPT_PPN_MASK_32;\n+ } else if (riscv_cpu_xlen(env) == 64) {\n+ mode_value = (val & MMPT_MODE_MASK_64) >> MMPT_MODE_SHIFT_64;\n+ if (mode_value == SMMPTBARE) {\n+ goto set_remaining_fields_zero;\n+ } else if (mode_value < SMMPTMAX) {\n+ /* convert to mpt_mode_t */\n+ mode_value += SMMPT43 - SMMPT34;\n+ env->mptmode = mode_value;\n+ }\n+ env->sdid = (val & MMPT_SDID_MASK_64) >> MMPT_SDID_SHIFT_64;\n+ env->mptppn = val & MMPT_PPN_MASK_64;\n+ } else {\n+ return RISCV_EXCP_ILLEGAL_INST;\n+ }\n+ return RISCV_EXCP_NONE;\n+\n+set_remaining_fields_zero:\n+ env->sdid = 0;\n+ env->mptmode = SMMPTBARE;\n+ env->mptppn = 0;\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static RISCVException read_msdcfg(CPURISCVState *env, int csrno,\n+ target_ulong *val)\n+{\n+ *val = env->msdcfg;\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static RISCVException write_msdcfg(CPURISCVState *env, int csrno,\n+ target_ulong val, uintptr_t ra)\n+{\n+ env->msdcfg = val;\n+ return RISCV_EXCP_NONE;\n+}\n+\n #endif\n \n /* Crypto Extension */\n@@ -6660,6 +6752,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {\n write_mhpmcounterh },\n [CSR_SCOUNTOVF] = { \"scountovf\", sscofpmf, read_scountovf,\n .min_priv_ver = PRIV_VERSION_1_12_0 },\n+ /* Supervisor Domain Identifier and Protection Registers */\n+ [CSR_MMPT] = { \"mmpt\", smsdid, read_mmpt, write_mmpt },\n+ [CSR_MSDCFG] = { \"msdcfg\", smsdid, read_msdcfg, write_msdcfg },\n \n #endif /* !CONFIG_USER_ONLY */\n };\ndiff --git a/target/riscv/riscv_smmpt.h b/target/riscv/riscv_smmpt.h\nnew file mode 100644\nindex 0000000000..74dcccf4be\n--- /dev/null\n+++ b/target/riscv/riscv_smmpt.h\n@@ -0,0 +1,21 @@\n+/*\n+ * QEMU RISC-V Smmpt (Memory Protection Table)\n+ *\n+ * Copyright (c) 2024 Alibaba Group. All rights reserved.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef RISCV_SMMPT_H\n+#define RISCV_SMMPT_H\n+\n+typedef enum {\n+ SMMPTBARE = 0,\n+ SMMPT34 = 1,\n+ SMMPT43 = 2,\n+ SMMPT52 = 3,\n+ SMMPT64 = 4,\n+ SMMPTMAX\n+} mpt_mode_t;\n+\n+#endif\n","prefixes":["v5","1/6"]}