{"id":2221138,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221138/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408140635.42546-5-zhiwei_liu@linux.alibaba.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408140635.42546-5-zhiwei_liu@linux.alibaba.com>","date":"2026-04-08T14:06:33","name":"[v5,4/6] target/riscv: Implement SMMPT fence instructions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ff9018b7bfa6d366a43059569b8a9a4f8b6fa892","submitter":{"id":84720,"url":"http://patchwork.ozlabs.org/api/1.1/people/84720/?format=json","name":"LIU Zhiwei","email":"zhiwei_liu@linux.alibaba.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408140635.42546-5-zhiwei_liu@linux.alibaba.com/mbox/","series":[{"id":499183,"url":"http://patchwork.ozlabs.org/api/1.1/series/499183/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499183","date":"2026-04-08T14:06:34","name":"target/riscv: Implement Smsdid and Smmpt extension","version":5,"mbox":"http://patchwork.ozlabs.org/series/499183/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221138/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221138/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default header.b=TTSATh8Q;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed;\n d=linux.alibaba.com; s=default;\n t=1775657328; h=From:To:Subject:Date:Message-Id:MIME-Version;\n bh=7btD77cTka+EC1KtIs9mPj6vd0anECLAhodJnjQttdc=;\n b=TTSATh8QpBgLjz7ojaxiYOnEiJI+1kmhoXAsBKGzboZxtVCwwqhg82FowFYc36q9BYAt6NGH0e69QNMqzfESECbMBQGjyrTHPcTcVJjZfJyvVE675JwpaX7WxxUiGKqSlX0su/4JfvY65OGQSLnQkzsnef49vZFzt6o5ceXfNAM=","X-Alimail-AntiSpam":"AC=PASS; BC=-1|-1; BR=01201311R201e4; CH=green;\n DM=||false|;\n DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033032089153;\n MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=11; SR=0;\n TI=SMTPD_---0X0f.zj4_1775657327;","From":"LIU Zhiwei ","To":"qemu-devel@nongnu.org","Cc":"qemu-riscv@nongnu.org, chao.liu.zevorn@gmail.com, palmer@dabbelt.com,\n alistair23@gmail.com, daniel.barboza@oss.qualcomm.com, liwei1518@gmail.com,\n LIU Zhiwei ,\n Huang Tao ,\n TANG Tiancheng ,\n Daniel Henrique Barboza ","Subject":"[PATCH v5 4/6] target/riscv: Implement SMMPT fence instructions","Date":"Wed, 8 Apr 2026 22:06:33 +0800","Message-Id":"<20260408140635.42546-5-zhiwei_liu@linux.alibaba.com>","X-Mailer":"git-send-email 2.39.3 (Apple Git-146)","In-Reply-To":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>","References":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=115.124.30.119;\n envelope-from=zhiwei_liu@linux.alibaba.com;\n helo=out30-119.freemail.mail.aliyun.com","X-Spam_score_int":"-174","X-Spam_score":"-17.5","X-Spam_bar":"-----------------","X-Spam_report":"(-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5,\n USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This patch completes the SMMPT implementation by adding support for the\nnew fence instructions: `mfence.spa` and `minval.spa`.\n\nAccording to the specification, these instructions act as memory ordering\nfences for MPT updates. In QEMU's TCG model, this is conservatively\nimplemented by flushing the entire TLB, which ensures that any subsequent\nmemory accesses will re-evaluate permissions and see the effects of any prior\nMPT modifications.\n\nThe instructions are privileged and will cause an illegal instruction\nexception if executed outside of M-mode.\n\nCo-authored-by: Huang Tao \nCo-authored-by: TANG Tiancheng \nSigned-off-by: LIU Zhiwei \nReviewed-by: Daniel Henrique Barboza \n---\n target/riscv/insn32.decode | 2 ++\n .../riscv/insn_trans/trans_privileged.c.inc | 30 +++++++++++++++++++\n 2 files changed, 32 insertions(+)","diff":"diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode\nindex 6e35c4b1e6..84cec57daf 100644\n--- a/target/riscv/insn32.decode\n+++ b/target/riscv/insn32.decode\n@@ -120,6 +120,8 @@ sret 0001000 00010 00000 000 00000 1110011\n mret 0011000 00010 00000 000 00000 1110011\n wfi 0001000 00101 00000 000 00000 1110011\n sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma\n+mfence_spa 1000011 ..... ..... 000 00000 1110011 @sfence_vma\n+minval_spa 0000011 ..... ..... 000 00000 1110011 @sfence_vma\n \n # *** NMI ***\n mnret 0111000 00010 00000 000 00000 1110011\ndiff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc\nindex 8a62b4cfcd..5ec6bf5991 100644\n--- a/target/riscv/insn_trans/trans_privileged.c.inc\n+++ b/target/riscv/insn_trans/trans_privileged.c.inc\n@@ -160,3 +160,33 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)\n #endif\n return false;\n }\n+\n+#define REQUIRE_SMSDID(ctx) do { \\\n+ if (!ctx->cfg_ptr->ext_smsdid) { \\\n+ return false; \\\n+ } \\\n+} while (0)\n+\n+static bool do_mfence_spa(DisasContext *ctx)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ REQUIRE_SMSDID(ctx);\n+ if (ctx->priv != PRV_M) {\n+ return false;\n+ }\n+ decode_save_opc(ctx, 0);\n+ gen_helper_tlb_flush_all(tcg_env);\n+ return true;\n+#endif\n+ return false;\n+}\n+\n+static bool trans_mfence_spa(DisasContext *ctx, arg_mfence_spa *a)\n+{\n+ return do_mfence_spa(ctx);\n+}\n+\n+static bool trans_minval_spa(DisasContext *ctx, arg_minval_spa *a)\n+{\n+ return do_mfence_spa(ctx);\n+}\n","prefixes":["v5","4/6"]}