{"id":2221135,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221135/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408042149.1902796-5-brian.cain@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408042149.1902796-5-brian.cain@oss.qualcomm.com>","date":"2026-04-08T04:21:43","name":"[v4,4/9] hw/hexagon: Add v68, sa8775-cdsp0 defs","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"672dca5415276962d60f2f665f4aefc23f420c23","submitter":{"id":89839,"url":"http://patchwork.ozlabs.org/api/1.1/people/89839/?format=json","name":"Brian Cain","email":"brian.cain@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408042149.1902796-5-brian.cain@oss.qualcomm.com/mbox/","series":[{"id":499184,"url":"http://patchwork.ozlabs.org/api/1.1/series/499184/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499184","date":"2026-04-08T04:21:47","name":"Hexagon system emulation - Part 3/3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499184/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221135/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221135/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 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envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Brian Cain \n\nAcked-by: Taylor Simpson \nSigned-off-by: Brian Cain \n---\n hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc | 64 ++++++++++++++++++++++\n hw/hexagon/machine_cfg_v68n_1024.h.inc | 65 +++++++++++++++++++++++\n 2 files changed, 129 insertions(+)\n create mode 100644 hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc\n create mode 100644 hw/hexagon/machine_cfg_v68n_1024.h.inc","diff":"diff --git a/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc b/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc\nnew file mode 100644\nindex 00000000000..442cbe3be31\n--- /dev/null\n+++ b/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+static const struct hexagon_machine_config SA8775P_cdsp0 = {\n+ .cfgbase = 0x24000000 + 0x180000,\n+ .l2tcm_size = 0x00000000,\n+ .l2vic_base = 0x26300000 + 0x90000,\n+ .l2vic_size = 0x00001000,\n+ .csr_base = 0x26300000,\n+ .qtmr_region = 0x26300000 + 0xA1000,\n+ .cfgtable = {\n+ .l2tcm_base = 0x00002400,\n+ .reserved0 = 0x00000000,\n+ .subsystem_base = 0x00002638,\n+ .etm_base = 0x00002419,\n+ .l2cfg_base = 0x0000241a,\n+ .reserved1 = 0x0000241b,\n+ .l1s0_base = 0x00002500,\n+ .axi2_lowaddr = 0x00000000,\n+ .streamer_base = 0x00000000,\n+ .reserved2 = 0x00000000,\n+ .fastl2vic_base = 0x0000241e,\n+ .jtlb_size_entries = 0x00000080,\n+ .coproc_present = 0x00000001,\n+ .ext_contexts = 0x00000004,\n+ .vtcm_base = 0x00002500,\n+ .vtcm_size_kb = 0x00002000,\n+ .l2tag_size = 0x00000400,\n+ .l2ecomem_size = 0x00000000,\n+ .thread_enable_mask = 0x0000003f,\n+ .eccreg_base = 0x0000241f,\n+ .l2line_size = 0x00000080,\n+ .tiny_core = 0x00000000,\n+ .l2itcm_size = 0x00000000,\n+ .l2itcm_base = 0x00002400,\n+ .reserved3 = 0x00000000,\n+ .dtm_present = 0x00000000,\n+ .dma_version = 0x00000003,\n+ .hvx_vec_log_length = 0x00000007,\n+ .core_id = 0x00000000,\n+ .core_count = 0x00000000,\n+ .coproc2_reg0 = 0x00000040,\n+ .coproc2_reg1 = 0x00000020,\n+ .v2x_mode = 0x00000001,\n+ .coproc2_reg2 = 0x00000008,\n+ .coproc2_reg3 = 0x00000020,\n+ .coproc2_reg4 = 0x00000000,\n+ .coproc2_reg5 = 0x00000002,\n+ .coproc2_reg6 = 0x00000016,\n+ .coproc2_reg7 = 0x00000006,\n+ .acd_preset = 0x00000001,\n+ .mnd_preset = 0x00000000,\n+ .l1d_size_kb = 0x00000010,\n+ .l1i_size_kb = 0x00000020,\n+ .l1d_write_policy = 0x00000002,\n+ .vtcm_bank_width = 0x00000080,\n+ .reserved4 = 0x00000001,\n+ .reserved5 = 0x00000000,\n+ .reserved6 = 0x00000003,\n+ .coproc2_cvt_mpy_size = 0x0000000a,\n+ .consistency_domain = 0x000000e0,\n+ .capacity_domain = 0x00000080,\n+ .axi3_lowaddr = 0x00000000,\n+ },\n+};\ndiff --git a/hw/hexagon/machine_cfg_v68n_1024.h.inc b/hw/hexagon/machine_cfg_v68n_1024.h.inc\nnew file mode 100644\nindex 00000000000..82619c42ac1\n--- /dev/null\n+++ b/hw/hexagon/machine_cfg_v68n_1024.h.inc\n@@ -0,0 +1,65 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+static const struct hexagon_machine_config v68n_1024 = {\n+ .cfgbase = 0xde000000,\n+ .l2tcm_size = 0x00000000,\n+ .l2vic_base = 0xfc910000,\n+ .l2vic_size = 0x00001000,\n+ .csr_base = 0xfc900000,\n+ .qtmr_region = 0xfc921000,\n+ .cfgtable = {\n+ .l2tcm_base = 0x0000d800,\n+ .reserved0 = 0x00000000,\n+ .subsystem_base = 0x0000fc90,\n+ .etm_base = 0x0000d819,\n+ .l2cfg_base = 0x0000d81a,\n+ .reserved1 = 0x00000000,\n+ .l1s0_base = 0x0000d840,\n+ .axi2_lowaddr = 0x00003000,\n+ .streamer_base = 0x0000d81c,\n+ .reserved2 = 0x0000d81d,\n+ .fastl2vic_base = 0x0000d81e,\n+ .jtlb_size_entries = 0x00000080,\n+ .coproc_present = 0x00000001,\n+ .ext_contexts = 0x00000004,\n+ .vtcm_base = 0x0000d840,\n+ .vtcm_size_kb = 0x00001000,\n+ .l2tag_size = 0x00000400,\n+ .l2ecomem_size = 0x00000400,\n+ .thread_enable_mask = 0x0000003f,\n+ .eccreg_base = 0x0000d81f,\n+ .l2line_size = 0x00000080,\n+ .tiny_core = 0x00000000,\n+ .l2itcm_size = 0x00000000,\n+ .l2itcm_base = 0x0000d820,\n+ .reserved3 = 0x00000000,\n+ .dtm_present = 0x00000000,\n+ .dma_version = 0x00000001,\n+ .hvx_vec_log_length = 0x00000007,\n+ .core_id = 0x00000000,\n+ .core_count = 0x00000000,\n+ .coproc2_reg0 = 0x00000040,\n+ .coproc2_reg1 = 0x00000020,\n+ .v2x_mode = 0x1f1f1f1f,\n+ .coproc2_reg2 = 0x1f1f1f1f,\n+ .coproc2_reg3 = 0x1f1f1f1f,\n+ .coproc2_reg4 = 0x1f1f1f1f,\n+ .coproc2_reg5 = 0x1f1f1f1f,\n+ .coproc2_reg6 = 0x1f1f1f1f,\n+ .coproc2_reg7 = 0x1f1f1f1f,\n+ .acd_preset = 0x1f1f1f1f,\n+ .mnd_preset = 0x1f1f1f1f,\n+ .l1d_size_kb = 0x1f1f1f1f,\n+ .l1i_size_kb = 0x1f1f1f1f,\n+ .l1d_write_policy = 0x1f1f1f1f,\n+ .vtcm_bank_width = 0x1f1f1f1f,\n+ .reserved4 = 0x1f1f1f1f,\n+ .reserved5 = 0x1f1f1f1f,\n+ .reserved6 = 0x1f1f1f1f,\n+ .coproc2_cvt_mpy_size = 0x1f1f1f1f,\n+ .consistency_domain = 0x1f1f1f1f,\n+ .capacity_domain = 0x1f1f1f1f,\n+ .axi3_lowaddr = 0x1f1f1f1f,\n+ },\n+};\n+\n","prefixes":["v4","4/9"]}