{"id":2221134,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221134/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407222208.271838-16-pierrick.bouvier@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260407222208.271838-16-pierrick.bouvier@linaro.org>","date":"2026-04-07T22:22:02","name":"[v11,15/21] target/arm/tcg/translate.c: replace TCGv with TCGv_va","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"43d6db1b859699cffe62ed44fd7908c498652aa1","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/1.1/people/85798/?format=json","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407222208.271838-16-pierrick.bouvier@linaro.org/mbox/","series":[{"id":499177,"url":"http://patchwork.ozlabs.org/api/1.1/series/499177/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499177","date":"2026-04-07T22:21:55","name":"target/arm: single-binary","version":11,"mbox":"http://patchwork.ozlabs.org/series/499177/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221134/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221134/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Qa/eSDJP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x532.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"We know this file is for 32-bit runtime target, so we can set\nTCG_ADDRESS_BITS. TCG_TYPE_VA is derived accordingly and is already\npassed to translator_loop.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Pierrick Bouvier \n---\n target/arm/tcg/translate.c | 29 +++++++++++++++--------------\n 1 file changed, 15 insertions(+), 14 deletions(-)","diff":"diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex fa4c7907dcd..0b3b4ab86be 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -22,7 +22,8 @@\n \n #include \"translate.h\"\n #include \"translate-a32.h\"\n-#include \"tcg/tcg-op.h\"\n+#define TCG_ADDRESS_BITS 32\n+#include \"tcg/tcg-op-mem.h\"\n #include \"qemu/log.h\"\n #include \"arm_ldst.h\"\n #include \"semihosting/semihost.h\"\n@@ -910,14 +911,14 @@ MemOp pow2_align(unsigned i)\n * that the address argument is TCGv_i32 rather than TCGv.\n */\n \n-static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n+static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n {\n- TCGv addr = tcg_temp_new();\n- tcg_gen_extu_i32_tl(addr, a32);\n+ TCGv_va addr = tcgv_va_temp_new();\n+ tcg_gen_mov_i32(addr, a32);\n \n /* Not needed for user-mode BE32, where we use MO_BE instead. */\n if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {\n- tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));\n+ tcg_gen_xori_i32(addr, addr, 4 - (1 << (op & MO_SIZE)));\n }\n return addr;\n }\n@@ -929,21 +930,21 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n tcg_gen_qemu_ld_i32(val, addr, index, opc);\n }\n \n void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n tcg_gen_qemu_st_i32(val, addr, index, opc);\n }\n \n void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n \n tcg_gen_qemu_ld_i64(val, addr, index, opc);\n \n@@ -956,7 +957,7 @@ void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,\n void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n \n /* Not needed for user-mode BE32, where we use MO_BE instead. */\n if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {\n@@ -2036,7 +2037,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,\n * architecturally 64-bit access, but instead do a 64-bit access\n * using MO_BE if appropriate and then split the two halves.\n */\n- TCGv taddr = gen_aa32_addr(s, addr, opc);\n+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);\n \n tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc);\n tcg_gen_mov_i64(cpu_exclusive_val, t64);\n@@ -2065,7 +2066,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n {\n TCGv_i32 t0, t1, t2;\n TCGv_i64 extaddr;\n- TCGv taddr;\n+ TCGv_va taddr;\n TCGLabel *done_label;\n TCGLabel *fail_label;\n MemOp opc = size | MO_ALIGN | s->be_data;\n@@ -3792,7 +3793,7 @@ static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)\n */\n int mem_idx = get_mem_index(s);\n MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;\n- TCGv taddr = gen_aa32_addr(s, addr, opc);\n+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);\n TCGv_i64 t64 = tcg_temp_new_i64();\n TCGv_i32 tmp = tcg_temp_new_i32();\n TCGv_i32 tmp2 = tcg_temp_new_i32();\n@@ -3847,7 +3848,7 @@ static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2)\n */\n int mem_idx = get_mem_index(s);\n MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;\n- TCGv taddr = gen_aa32_addr(s, addr, opc);\n+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);\n TCGv_i32 t1 = load_reg(s, rt);\n TCGv_i32 t2 = load_reg(s, rt2);\n TCGv_i64 t64 = tcg_temp_new_i64();\n@@ -4068,7 +4069,7 @@ DO_LDST(STRH, store, MO_UW)\n static bool op_swp(DisasContext *s, arg_SWP *a, MemOp opc)\n {\n TCGv_i32 addr, tmp;\n- TCGv taddr;\n+ TCGv_va taddr;\n \n opc |= s->be_data;\n addr = load_reg(s, a->rn);\n","prefixes":["v11","15/21"]}