{"id":2221081,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221081/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260408-jk-even-more-e825c-fixes-v1-2-b959da91a81f@intel.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/1.1/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408-jk-even-more-e825c-fixes-v1-2-b959da91a81f@intel.com>","date":"2026-04-08T18:46:32","name":"[iwl-net,2/4] ice: perform PHY soft reset for E825C ports at initialization","commit_ref":null,"pull_url":null,"state":"under-review","archived":false,"hash":"b7b0f43f550b40a4f44762652cc7c0ad00d9a27f","submitter":{"id":9784,"url":"http://patchwork.ozlabs.org/api/1.1/people/9784/?format=json","name":"Jacob Keller","email":"jacob.e.keller@intel.com"},"delegate":{"id":109701,"url":"http://patchwork.ozlabs.org/api/1.1/users/109701/?format=json","username":"anguy11","first_name":"Anthony","last_name":"Nguyen","email":"anthony.l.nguyen@intel.com"},"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260408-jk-even-more-e825c-fixes-v1-2-b959da91a81f@intel.com/mbox/","series":[{"id":499189,"url":"http://patchwork.ozlabs.org/api/1.1/series/499189/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=499189","date":"2026-04-08T18:46:30","name":"ice: E825C missing PHY timestamp interrupt fixes","version":1,"mbox":"http://patchwork.ozlabs.org/series/499189/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221081/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221081/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=3mTnziZN;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::136; 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a=\"75841388\"","E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"75841388\"","E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"230217563\""],"X-ExtLoop1":"1","From":"Jacob Keller ","Date":"Wed, 08 Apr 2026 11:46:32 -0700","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260408-jk-even-more-e825c-fixes-v1-2-b959da91a81f@intel.com>","References":"<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>","In-Reply-To":"<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>","To":"Anthony Nguyen ,\n Intel Wired LAN , netdev@vger.kernel.org","X-Mailer":"b4 0.16-dev-306a9","X-Developer-Signature":"v=1; a=openpgp-sha256; l=7639;\n i=jacob.e.keller@intel.com; h=from:subject:message-id;\n bh=tvvenahFztgo1FeA+D0zmawzjSttw0Lv5ZsSN3NC/+o=;\n b=owGbwMvMwCWWNS3WLp9f4wXjabUkhsxri/aEeG/kuXRq0lIeWc57atOaIx/NOmCkdIAjbvql3\n tmx32ynd5SyMIhxMciKKbIoOISsvG48IUzrjbMczBxWJpAhDFycAjCRyesY/vuvUlssafVr18Mv\n ChOXLZyjzMVe+kS9bPfK4O3Zh05f0vrG8D+1I/T224XTZ+ect/zP0WfTuvgbO4fdJmmRc/Vafee\n MEzgA","X-Developer-Key":"i=jacob.e.keller@intel.com; a=openpgp;\n fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775674049; x=1807210049;\n h=from:date:subject:mime-version:content-transfer-encoding:\n message-id:references:in-reply-to:to:cc;\n bh=b9RwiRxpk38kPQPs+FH1DQizAozd96iPnz/ykGFJxI8=;\n b=Kr71/8yfPmcgIJgvA/pZe+EUOofH+1/obQ28CvVeC+f/G1DSUoIICMgn\n /dDXS8l1B1db9jeE82x1mPpDZBKl/y7hBuUuq66WMI1Jy0uWaj5D1JlZa\n dHLWpUrd9SEQ0wI1wLxGG+tm3FgQma8yJL5xkx/7KuuKi5cc2rti4zVdU\n 5ugY6WoG4GPVcKERMksvFlmo8y4hb9Ieu1As8WqjjNhKtdn+34cQBOtYh\n LmP9KkP1xa5VM1CF1qR2egcaruXty0b8BrBaDHsN0pr+foULmmwRkw2sc\n idZyiCV2d7GboS7zbzTG4ENMwfiNdBVxWpZVK6c29HXwg5hhnorn1z3j6\n w==;","X-Mailman-Original-Authentication-Results":["smtp3.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp3.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=Kr71/8yf"],"Subject":"[Intel-wired-lan] [PATCH iwl-net 2/4] ice: perform PHY soft reset\n for E825C ports at initialization","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"Aleksandr Loktionov ,\n Jacob Keller ,\n Timothy Miskell ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"From: Grzegorz Nitka \n\nIn some cases the PHY timestamp block of the E825C can become stuck. This\nis known to occur if the software writes 0 to the Tx timestamp threshold,\nand with older versions of the ice driver the threshold configuration is\nbuggy and can race in such that hardware briefly operates with a zero\nthreshold enabled. There are no other known ways to trigger this behavior,\nbut once it occurs, the hardware is not recovered by normal reset, a driver\nreload, or even a warm power cycle of the system. A cold power cycle is\nsufficient to recover hardware, but this is extremely invasive and can\nresult in significant downtime on customer deployments.\n\nThe PHY for each port has a timestamping block which has its own reset\nfunctionality accessible by programming the PHY_REG_GLOBAL register.\nWriting to the PHY_REG_GLOBAL_SOFT_RESET_BIT triggers the hardware to\nperform a complete reset of the timestamping block of the PHY. This\nincludes clearing the timestamp status for the port, clearing all\noutstanding timestamps in the memory bank, and resetting the PHY timer.\n\nThe new ice_ptp_phy_soft_reset_eth56g() function toggles the\nPHY_REG_GLOBAL soft reset bit with the required delays, ensuring the\nPHY is properly reinitialized without requiring a full device reset.\nThe sequence clears the reset bit, asserts it, then clears it again,\nwith short waits between transitions to allow hardware stabilization.\n\nCall this function in the new ice_ptp_init_phc_e825c(), implementing the\nE825C device specific variant of the ice_ptp_init_phc(). Note that if\nice_ptp_init_phc() fails, PTP functionality may be disabled, but the driver\nwill still load to allow basic functionality to continue.\n\nThis causes the clock owning PF driver to perform a PHY soft reset for\nevery port during initialization. This ensures the driver begins life in a\nknown functional state regardless of how it was previously programmed.\n\nThis ensures that we properly reconfigure the hardware after a device reset\nor when loading the driver, even if it was previously misconfigured with an\nout-of-date or modified driver.\n\nFixes: 7cab44f1c35f (\"ice: Introduce ETH56G PHY model for E825C products\")\nSigned-off-by: Timothy Miskell \nSigned-off-by: Grzegorz Nitka \nSigned-off-by: Jacob Keller \nReviewed-by: Aleksandr Loktionov \n---\n drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 ++\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 90 ++++++++++++++++++++++++++++-\n 2 files changed, 93 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\nindex 5896b346e579..9d7acc7eb2ce 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\n@@ -374,6 +374,7 @@ int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);\n int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);\n int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);\n int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);\n+int ice_ptp_phy_soft_reset_eth56g(struct ice_hw *hw, u8 port);\n \n #define ICE_ETH56G_NOMINAL_INCVAL\t0x140000000ULL\n #define ICE_ETH56G_NOMINAL_PCS_REF_TUS\t0x100000000ULL\n@@ -676,6 +677,9 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw)\n #define ICE_P0_GNSS_PRSNT_N\tBIT(4)\n \n /* ETH56G PHY register addresses */\n+#define PHY_REG_GLOBAL\t\t\t0x0\n+#define PHY_REG_GLOBAL_SOFT_RESET_M\tBIT(11)\n+\n /* Timestamp PHY incval registers */\n #define PHY_REG_TIMETUS_L\t\t0x8\n #define PHY_REG_TIMETUS_U\t\t0xC\ndiff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\nindex 67775beb9449..441b5f10e4bb 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n@@ -377,6 +377,31 @@ static void ice_ptp_cfg_sync_delay(const struct ice_hw *hw, u32 delay)\n * The following functions operate on devices with the ETH 56G PHY.\n */\n \n+/**\n+ * ice_ptp_init_phc_e825c - Perform E825C specific PHC initialization\n+ * @hw: pointer to HW struct\n+ *\n+ * Perform E825C-specific PTP hardware clock initialization steps.\n+ *\n+ * Return: 0 on success, or a negative error value on failure.\n+ */\n+static int ice_ptp_init_phc_e825c(struct ice_hw *hw)\n+{\n+\tint err;\n+\n+\t/* Soft reset all ports, to ensure everything is at a clean state */\n+\tfor (int port = 0; port < hw->ptp.num_lports; port++) {\n+\t\terr = ice_ptp_phy_soft_reset_eth56g(hw, port);\n+\t\tif (err) {\n+\t\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to soft reset port %d, err %d\\n\",\n+\t\t\t\t port, err);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n /**\n * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number\n * @hw: pointer to the HW struct\n@@ -2179,6 +2204,69 @@ int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)\n \treturn 0;\n }\n \n+/**\n+ * ice_ptp_phy_soft_reset_eth56g - Perform a PHY soft reset on ETH56G\n+ * @hw: pointer to the HW structure\n+ * @port: PHY port number\n+ *\n+ * Trigger a soft reset of the ETH56G PHY by toggling the soft reset\n+ * bit in the PHY global register. The reset sequence consists of:\n+ * 1. Clearing the soft reset bit\n+ * 2. Asserting the soft reset bit\n+ * 3. Clearing the soft reset bit again\n+ *\n+ * Short delays are inserted between each step to allow the hardware\n+ * to settle. This provides a controlled way to reinitialize the PHY\n+ * without requiring a full device reset.\n+ *\n+ * Return: 0 on success, or a negative error code on failure when\n+ * reading or writing the PHY register.\n+ */\n+int ice_ptp_phy_soft_reset_eth56g(struct ice_hw *hw, u8 port)\n+{\n+\tu32 global_val;\n+\tint err;\n+\n+\terr = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, &global_val);\n+\tif (err) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read PHY_REG_GLOBAL for port %d, err %d\\n\",\n+\t\t\t port, err);\n+\t\treturn err;\n+\t}\n+\n+\tglobal_val &= ~PHY_REG_GLOBAL_SOFT_RESET_M;\n+\tice_debug(hw, ICE_DBG_PTP, \"Clearing soft reset bit for port %d, val: 0x%x\\n\",\n+\t\t port, global_val);\n+\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val);\n+\tif (err) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write PHY_REG_GLOBAL for port %d, err %d\\n\",\n+\t\t\t port, err);\n+\t\treturn err;\n+\t}\n+\n+\tusleep_range(5000, 6000);\n+\n+\tglobal_val |= PHY_REG_GLOBAL_SOFT_RESET_M;\n+\tice_debug(hw, ICE_DBG_PTP, \"Set soft reset bit for port %d, val: 0x%x\\n\",\n+\t\t port, global_val);\n+\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val);\n+\tif (err) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write PHY_REG_GLOBAL for port %d, err %d\\n\",\n+\t\t\t port, err);\n+\t\treturn err;\n+\t}\n+\tusleep_range(5000, 6000);\n+\n+\tglobal_val &= ~PHY_REG_GLOBAL_SOFT_RESET_M;\n+\tice_debug(hw, ICE_DBG_PTP, \"Clear soft reset bit for port %d, val: 0x%x\\n\",\n+\t\t port, global_val);\n+\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val);\n+\tif (err)\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write PHY_REG_GLOBAL for port %d, err %d\\n\",\n+\t\t\t port, err);\n+\treturn err;\n+}\n+\n /**\n * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register\n * @hw: pointer to the HW struct\n@@ -5591,7 +5679,7 @@ int ice_ptp_init_phc(struct ice_hw *hw)\n \tcase ICE_MAC_GENERIC:\n \t\treturn ice_ptp_init_phc_e82x(hw);\n \tcase ICE_MAC_GENERIC_3K_E825:\n-\t\treturn 0;\n+\t\treturn ice_ptp_init_phc_e825c(hw);\n \tdefault:\n \t\treturn -EOPNOTSUPP;\n \t}\n","prefixes":["iwl-net","2/4"]}