{"id":2221079,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221079/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260408-jk-even-more-e825c-fixes-v1-1-b959da91a81f@intel.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/1.1/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408-jk-even-more-e825c-fixes-v1-1-b959da91a81f@intel.com>","date":"2026-04-08T18:46:31","name":"[iwl-net,1/4] ice: fix timestamp interrupt configuration for E825C","commit_ref":null,"pull_url":null,"state":"under-review","archived":false,"hash":"1b0ad3689e274048835a22ebd0a00d1894f9c51b","submitter":{"id":9784,"url":"http://patchwork.ozlabs.org/api/1.1/people/9784/?format=json","name":"Jacob Keller","email":"jacob.e.keller@intel.com"},"delegate":{"id":109701,"url":"http://patchwork.ozlabs.org/api/1.1/users/109701/?format=json","username":"anguy11","first_name":"Anthony","last_name":"Nguyen","email":"anthony.l.nguyen@intel.com"},"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260408-jk-even-more-e825c-fixes-v1-1-b959da91a81f@intel.com/mbox/","series":[{"id":499189,"url":"http://patchwork.ozlabs.org/api/1.1/series/499189/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=499189","date":"2026-04-08T18:46:30","name":"ice: E825C missing PHY timestamp interrupt fixes","version":1,"mbox":"http://patchwork.ozlabs.org/series/499189/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221079/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221079/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=nT7eG/FQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::136; 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a=\"75841386\"","E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"75841386\"","E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"230217560\""],"X-ExtLoop1":"1","From":"Jacob Keller ","Date":"Wed, 08 Apr 2026 11:46:31 -0700","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260408-jk-even-more-e825c-fixes-v1-1-b959da91a81f@intel.com>","References":"<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>","In-Reply-To":"<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>","To":"Anthony Nguyen ,\n Intel Wired LAN , netdev@vger.kernel.org","X-Mailer":"b4 0.16-dev-306a9","X-Developer-Signature":"v=1; a=openpgp-sha256; l=5492;\n i=jacob.e.keller@intel.com; h=from:subject:message-id;\n bh=RfOBce6ZBKcXPiiqDoqjeTQe/2/0bz7nXMgcDDG6AGY=;\n b=owGbwMvMwCWWNS3WLp9f4wXjabUkhsxri/bwJU5UC2bVt2Y99Vgl1PBVnsPk86mCnybF/k6c2\n +ZQJHa7o5SFQYyLQVZMkUXBIWTldeMJYVpvnOVg5rAygQxh4OIUgImw/Gb4p1/9vEdJ8wrDvR2m\n 28OvxCo6bzr5aY/De+eHoveNp2msvsjwVzRWRuuFz9tFe/mK9N1ef1r0um0PZz9rzesC14RvB3Z\n E8QIA","X-Developer-Key":"i=jacob.e.keller@intel.com; a=openpgp;\n fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775674049; x=1807210049;\n h=from:date:subject:mime-version:content-transfer-encoding:\n message-id:references:in-reply-to:to:cc;\n bh=K3UN4pf9JPW3ZpduY02DTj0XVgO7vI4d+ii+qU3c24E=;\n b=gzGduOo6wKFssaTp6DqqrqkSprUiBwCmWuGceed/ZR81NMt6Y82sbUmT\n UvAnmlkOCc3JVMHuIsd/1sLhxeRftLBck+cJlGYxedluxmlf6nLBBnFuw\n Ct36TYBgqCoNFcq9S9uUWnSp+iEweWldHQ0PhiZqxQvNxJT18hjdTHaP2\n XkGGZlKLv5XGIL/hkzNZshoXv9CV1xNcG3jR0Jz9zdHG/DTE/7J4QJM+Y\n MC7eqoWm0g6C1/diVECdNkCvrMZXZHfeLrU3/6IdM6/6vkQ6Ot5iAKmux\n q1t7cuqJFuCYUDADYLaYqgFpFvSWEAZw4wJfu7nnpQM7kBQPL1mhTzNJl\n w==;","X-Mailman-Original-Authentication-Results":["smtp3.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp3.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=gzGduOo6"],"Subject":"[Intel-wired-lan] [PATCH iwl-net 1/4] ice: fix timestamp interrupt\n configuration for E825C","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"Aleksandr Loktionov ,\n Jacob Keller ,\n Timothy Miskell ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"From: Grzegorz Nitka \n\nThe E825C ice_phy_cfg_intr_eth56g() function is responsible for programming\nthe PHY interrupt for a given port. This function writes to the\nPHY_REG_TS_INT_CONFIG register of the port. The register is responsible for\nconfiguring whether the port interrupt logic is enabled, as well as\nprogramming the threshold of waiting timestamps that will trigger an\ninterrupt from this port.\n\nThis threshold value must not be programmed to zero while the interrupt is\nenabled. Doing so puts the port in a misconfigured state where the PHY\ntimestamp interrupt for the quad of connected ports will become stuck.\n\nThis occurs, because a threshold of zero results in the timestamp interrupt\nstatus for the port becoming stuck high. The four ports in the connected\nquad have their timestamp status indicators muxed together. A new interrupt\ncannot be generated until the timestamp status indicators return low for\nall four ports.\n\nNormally, the timestamp status for a port will clear once there are fewer\ntimestamps in that ports timestamp memory bank than the threshold. A\nthreshold of zero makes this impossible, so the timestamp status for the\nport does not clear.\n\nThe ice driver never intentionally programs the threshold to zero, indeed\nthe driver always programs it to a value of 1, intending to get an\ninterrupt immediately as soon as even a single packet is waiting for a\ntimestamp.\n\nHowever, there is a subtle flaw in the programming logic in the\nice_phy_cfg_intr_eth56g() function. Due to the way that the hardware\nhandles enabling the PHY interrupt. If the threshold value is modified at\nthe same time as the interrupt is enabled, the HW PHY state machine might\nenable the interrupt before the new threshold value is actually updated.\nThis leaves a potential race condition caused by the hardware logic where\na PHY timestamp interrupt might be triggered before the non-zero threshold\nis written, resulting in the PHY timestamp logic becoming stuck.\n\nOnce the PHY timestamp status is stuck high, it will remain stuck even\nafter attempting to reprogram the PHY block by changing its threshold or\ndisabling the interrupt. Even a typical PF or CORE reset will not reset the\nparticular block of the PHY that becomes stuck. Even a warm power cycle is\nnot guaranteed to cause the PHY block to reset, and a cold power cycle is\nrequired.\n\nPrevent this by always writing the PHY_REG_TS_INT_CONFIG in two stages.\nFirst write the threshold value with the interrupt disabled, and only write\nthe enable bit after the threshold has been programmed. When disabling the\ninterrupt, leave the threshold unchanged. Additionally, re-read the\nregister after writing it to guarantee that the write to the PHY has been\nflushed upon exit of the function.\n\nWhile we're modifying this function implementation, explicitly reject\nprogramming a threshold of 0 when enabling the interrupt. No caller does\nthis today, but the consequences of doing so are significant. An explicit\nrejection in the code makes this clear.\n\nFixes: 7cab44f1c35f (\"ice: Introduce ETH56G PHY model for E825C products\")\nSigned-off-by: Grzegorz Nitka \nSigned-off-by: Jacob Keller \nReviewed-by: Aleksandr Loktionov \n---\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 36 +++++++++++++++++++++++++----\n 1 file changed, 32 insertions(+), 4 deletions(-)","diff":"diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\nindex e3db252c3918..67775beb9449 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n@@ -1847,6 +1847,8 @@ static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port)\n * @ena: enable or disable interrupt\n * @threshold: interrupt threshold\n *\n+ * The threshold cannot be 0 while the interrupt is enabled.\n+ *\n * Configure TX timestamp interrupt for the specified port\n *\n * Return:\n@@ -1858,19 +1860,45 @@ int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold)\n \tint err;\n \tu32 val;\n \n+\tif (ena && !threshold)\n+\t\treturn -EINVAL;\n+\n \terr = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);\n \tif (err)\n \t\treturn err;\n \n+\tval &= ~PHY_TS_INT_CONFIG_ENA_M;\n \tif (ena) {\n-\t\tval |= PHY_TS_INT_CONFIG_ENA_M;\n \t\tval &= ~PHY_TS_INT_CONFIG_THRESHOLD_M;\n \t\tval |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold);\n-\t} else {\n-\t\tval &= ~PHY_TS_INT_CONFIG_ENA_M;\n+\t\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG,\n+\t\t\t\t\t val);\n+\t\tif (err) {\n+\t\t\tice_debug(hw, ICE_DBG_PTP,\n+\t\t\t\t \"Failed to update 'threshold' PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\\n\",\n+\t\t\t\t port, !!ena, threshold);\n+\t\t\treturn err;\n+\t\t}\n+\t\tval |= PHY_TS_INT_CONFIG_ENA_M;\n \t}\n \n-\treturn ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);\n+\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);\n+\tif (err) {\n+\t\tice_debug(hw, ICE_DBG_PTP,\n+\t\t\t \"Failed to update 'ena' PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\\n\",\n+\t\t\t port, !!ena, threshold);\n+\t\treturn err;\n+\t}\n+\n+\terr = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);\n+\tif (err) {\n+\t\tice_debug(hw, ICE_DBG_PTP,\n+\t\t\t \"Failed to read PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\\n\",\n+\t\t\t port, !!ena, threshold);\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n }\n \n /**\n","prefixes":["iwl-net","1/4"]}