{"id":2221077,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221077/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260408-jk-even-more-e825c-fixes-v1-4-b959da91a81f@intel.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/1.1/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408-jk-even-more-e825c-fixes-v1-4-b959da91a81f@intel.com>","date":"2026-04-08T18:46:34","name":"[iwl-net,4/4] ice: fix ice_ptp_read_tx_hwtstamp_status_eth56g","commit_ref":null,"pull_url":null,"state":"under-review","archived":false,"hash":"c34298c493c75ddc52655f4ec365d924a1e1bfe8","submitter":{"id":9784,"url":"http://patchwork.ozlabs.org/api/1.1/people/9784/?format=json","name":"Jacob Keller","email":"jacob.e.keller@intel.com"},"delegate":{"id":109701,"url":"http://patchwork.ozlabs.org/api/1.1/users/109701/?format=json","username":"anguy11","first_name":"Anthony","last_name":"Nguyen","email":"anthony.l.nguyen@intel.com"},"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260408-jk-even-more-e825c-fixes-v1-4-b959da91a81f@intel.com/mbox/","series":[{"id":499189,"url":"http://patchwork.ozlabs.org/api/1.1/series/499189/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=499189","date":"2026-04-08T18:46:30","name":"ice: E825C missing PHY timestamp interrupt fixes","version":1,"mbox":"http://patchwork.ozlabs.org/series/499189/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221077/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221077/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=gNFkh/9k;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::137; 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a=\"75841382\"","E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"75841382\"","E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"230217570\""],"X-ExtLoop1":"1","From":"Jacob Keller ","Date":"Wed, 08 Apr 2026 11:46:34 -0700","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260408-jk-even-more-e825c-fixes-v1-4-b959da91a81f@intel.com>","References":"<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>","In-Reply-To":"<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>","To":"Anthony Nguyen ,\n Intel Wired LAN , netdev@vger.kernel.org","X-Mailer":"b4 0.16-dev-306a9","X-Developer-Signature":"v=1; a=openpgp-sha256; l=1919;\n i=jacob.e.keller@intel.com; h=from:subject:message-id;\n bh=R6AxwX9GU8IMz9cc9hHesk4hswO49vClh2NXD0wCyaU=;\n b=owGbwMvMwCWWNS3WLp9f4wXjabUkhsxri/Y+bSrduCnDdYNNGJPPVBP12JaMpDUuKV9mhBSf5\n lS/e6Gmo5SFQYyLQVZMkUXBIWTldeMJYVpvnOVg5rAygQxh4OIUgIncn87wiyl3veh+2e1PH3JP\n NFr6wmrN072BHdc+fVv19YBH3oOvmr8YGd6s//mjPfNjgKXMGqG9XYfnMcSslPmd8VlFflkDC3N\n EECcA","X-Developer-Key":"i=jacob.e.keller@intel.com; a=openpgp;\n fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775674049; x=1807210049;\n h=from:date:subject:mime-version:content-transfer-encoding:\n message-id:references:in-reply-to:to:cc;\n bh=R6AxwX9GU8IMz9cc9hHesk4hswO49vClh2NXD0wCyaU=;\n b=WmVl2axIpajhgQfl9wz3i1FqVVUGYT9/BFTpFFxnc0+MqZjXQyf9a0pe\n BIT6yDXNXn8HqkHn2TKKqSzbe/TITvRJXyg3vliGF1q4Sckz7UpSiihkt\n UZyZLIYeJldUA6kBjtgBjfgpsAFi9J0/8j2xtT/kwia6ZswpO/nngioGO\n MvnmdPqe2KrCDZrbR0JTFNyjQPuxRnQFysvjq/hdjA4kMm+Q+dXlQHimk\n xqaSA48QLaSjJL2Ny8sPveeG0jp2VNlYmn6Fegc9Xp5uMRI8yrwC04gsJ\n WawptFwkhbq53ryDWm+mj91vjhv/w3DX7tfoZAVrbv83co6eRzvoiFPV9\n w==;","X-Mailman-Original-Authentication-Results":["smtp2.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp2.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=WmVl2axI"],"Subject":"[Intel-wired-lan] [PATCH iwl-net 4/4] ice: fix\n ice_ptp_read_tx_hwtstamp_status_eth56g","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"Aleksandr Loktionov ,\n Jacob Keller ,\n Timothy Miskell ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"The ice_ptp_read_tx_hwtstamp_status_eth56g function calls\nice_read_phy_eth56g with a PHY index. However the function actually expects\na port index. This causes the function to read the wrong PHY_PTP_INT_STATUS\nregisters, and effectively makes the status wrong for the second set of\nports from 4 to 7.\n\nThe ice_read_phy_eth56g function uses the provided port index to determine\nwhich PHY device to read. We could refactor the entire chain to take a PHY\nindex, but this would impact many code sites. Instead, multiply the PHY\nindex by the number of ports, so that we read from the first port of each\nPHY.\n\nFixes: 7cab44f1c35f (\"ice: Introduce ETH56G PHY model for E825C products\")\nSigned-off-by: Jacob Keller \nReviewed-by: Aleksandr Loktionov \n---\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\nindex 64ad5ed5c688..672218e5d1f9 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n@@ -2219,13 +2219,19 @@ int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)\n \t*ts_status = 0;\n \n \tfor (phy = 0; phy < params->num_phys; phy++) {\n+\t\tu8 port;\n \t\tint err;\n \n-\t\terr = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status);\n+\t\t/* ice_read_phy_eth56g expects a port index, so use the first\n+\t\t * port of the PHY\n+\t\t */\n+\t\tport = phy * hw->ptp.ports_per_phy;\n+\n+\t\terr = ice_read_phy_eth56g(hw, port, PHY_PTP_INT_STATUS, &status);\n \t\tif (err)\n \t\t\treturn err;\n \n-\t\t*ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy);\n+\t\t*ts_status |= (status & mask) << port;\n \t}\n \n \tice_debug(hw, ICE_DBG_PTP, \"PHY interrupt err: %x\\n\", *ts_status);\n","prefixes":["iwl-net","4/4"]}