{"id":2221065,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221065/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407222208.271838-2-pierrick.bouvier@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260407222208.271838-2-pierrick.bouvier@linaro.org>","date":"2026-04-07T22:21:48","name":"[v11,01/21] include/tcg/tcg-op: extract memory operations to tcg-op-mem.h","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c1b1dd5e6036f9fabb4d1d4acada93eb64651011","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/1.1/people/85798/?format=json","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407222208.271838-2-pierrick.bouvier@linaro.org/mbox/","series":[{"id":499177,"url":"http://patchwork.ozlabs.org/api/1.1/series/499177/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499177","date":"2026-04-07T22:21:55","name":"target/arm: single-binary","version":11,"mbox":"http://patchwork.ozlabs.org/series/499177/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221065/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221065/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=LdoOnDkj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::633;\n envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x633.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This new header defines a new type for target virtual address,\nindependent from TCGv and is parameterized by a new define\nTCG_ADDRESS_BITS (name was suggested by Paolo instead of\nTARGET_ADDRESS_BITS).\n\nBy default, tcg-op.h include set this define to TARGET_LONG_BITS, but\nit's also possible to include only tcg-op-common.h and tcg-op-mem.h and\nset TCG_ADDRESS_BITS manually, which is what next commits will do.\n\nWe preserve existing MIT license when extracting this new header.\n\nImplemented from:\nhttps://lore.kernel.org/qemu-devel/a68321f0-3d54-4909-864c-9793cda05b2a@linaro.org/\n\nSuggested-by: Richard Henderson \nReviewed-by: Philippe Mathieu-Daudé \nTested-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \nSigned-off-by: Pierrick Bouvier \n---\n include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++++++++++\n include/tcg/tcg-op.h | 100 +------------------------------\n 2 files changed, 129 insertions(+), 97 deletions(-)\n create mode 100644 include/tcg/tcg-op-mem.h","diff":"diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h\nnew file mode 100644\nindex 00000000000..36931d1dd57\n--- /dev/null\n+++ b/include/tcg/tcg-op-mem.h\n@@ -0,0 +1,126 @@\n+/* SPDX-License-Identifier: MIT */\n+/*\n+ * Target dependent memory related functions.\n+ *\n+ * Copyright (c) 2008 Fabrice Bellard\n+ */\n+\n+#ifndef TCG_TCG_OP_MEM_H\n+#define TCG_TCG_OP_MEM_H\n+\n+#ifndef TCG_ADDRESS_BITS\n+#error TCG_ADDRESS_BITS must be defined\n+#endif\n+\n+#if TCG_ADDRESS_BITS == 32\n+typedef TCGv_i32 TCGv_va;\n+#define TCG_TYPE_VA TCG_TYPE_I32\n+#define tcgv_va_temp tcgv_i32_temp\n+#define tcgv_va_temp_new tcg_temp_new_i32\n+#elif TCG_ADDRESS_BITS == 64\n+typedef TCGv_i64 TCGv_va;\n+#define TCG_TYPE_VA TCG_TYPE_I64\n+#define tcgv_va_temp tcgv_i64_temp\n+#define tcgv_va_temp_new tcg_temp_new_i64\n+#else\n+#error\n+#endif\n+\n+static inline void\n+tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m)\n+{\n+ tcg_gen_qemu_ld_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);\n+}\n+\n+static inline void\n+tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m)\n+{\n+ tcg_gen_qemu_st_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);\n+}\n+\n+static inline void\n+tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m)\n+{\n+ tcg_gen_qemu_ld_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);\n+}\n+\n+static inline void\n+tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m)\n+{\n+ tcg_gen_qemu_st_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);\n+}\n+\n+static inline void\n+tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m)\n+{\n+ tcg_gen_qemu_ld_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);\n+}\n+\n+static inline void\n+tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m)\n+{\n+ tcg_gen_qemu_st_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);\n+}\n+\n+#define DEF_ATOMIC2(N, S) \\\n+ static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S v, \\\n+ TCGArg i, MemOp m) \\\n+ { N##_##S##_chk(r, tcgv_va_temp(a), v, i, m, TCG_TYPE_VA); }\n+\n+#define DEF_ATOMIC3(N, S) \\\n+ static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S o, \\\n+ TCGv_##S n, TCGArg i, MemOp m) \\\n+ { N##_##S##_chk(r, tcgv_va_temp(a), o, n, i, m, TCG_TYPE_VA); }\n+\n+DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32)\n+DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64)\n+DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128)\n+\n+DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32)\n+DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64)\n+DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128)\n+\n+DEF_ATOMIC2(tcg_gen_atomic_xchg, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_xchg, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_xchg, i128)\n+\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i128)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i128)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64)\n+\n+DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64)\n+DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32)\n+DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)\n+\n+#undef DEF_ATOMIC2\n+#undef DEF_ATOMIC3\n+\n+#endif /* TCG_TCG_OP_MEM_H */\ndiff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h\nindex 7024be938e6..96a5af1a298 100644\n--- a/include/tcg/tcg-op.h\n+++ b/include/tcg/tcg-op.h\n@@ -16,6 +16,9 @@\n #error must include QEMU headers\n #endif\n \n+#define TCG_ADDRESS_BITS TARGET_LONG_BITS\n+#include \"tcg/tcg-op-mem.h\"\n+\n #if TARGET_LONG_BITS == 32\n # define TCG_TYPE_TL TCG_TYPE_I32\n #elif TARGET_LONG_BITS == 64\n@@ -46,103 +49,6 @@ typedef TCGv_i64 TCGv;\n #error Unhandled TARGET_LONG_BITS value\n #endif\n \n-static inline void\n-tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m)\n-{\n- tcg_gen_qemu_ld_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);\n-}\n-\n-static inline void\n-tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m)\n-{\n- tcg_gen_qemu_st_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);\n-}\n-\n-static inline void\n-tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m)\n-{\n- tcg_gen_qemu_ld_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);\n-}\n-\n-static inline void\n-tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m)\n-{\n- tcg_gen_qemu_st_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);\n-}\n-\n-static inline void\n-tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m)\n-{\n- tcg_gen_qemu_ld_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);\n-}\n-\n-static inline void\n-tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m)\n-{\n- tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);\n-}\n-\n-#define DEF_ATOMIC2(N, S) \\\n- static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S v, \\\n- TCGArg i, MemOp m) \\\n- { N##_##S##_chk(r, tcgv_tl_temp(a), v, i, m, TCG_TYPE_TL); }\n-\n-#define DEF_ATOMIC3(N, S) \\\n- static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S o, \\\n- TCGv_##S n, TCGArg i, MemOp m) \\\n- { N##_##S##_chk(r, tcgv_tl_temp(a), o, n, i, m, TCG_TYPE_TL); }\n-\n-DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32)\n-DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64)\n-DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128)\n-\n-DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32)\n-DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64)\n-DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128)\n-\n-DEF_ATOMIC2(tcg_gen_atomic_xchg, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_xchg, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_xchg, i128)\n-\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i128)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i128)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64)\n-\n-DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64)\n-DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32)\n-DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)\n-\n-#undef DEF_ATOMIC2\n-#undef DEF_ATOMIC3\n-\n #if TARGET_LONG_BITS == 64\n #define tcg_gen_movi_tl tcg_gen_movi_i64\n #define tcg_gen_mov_tl tcg_gen_mov_i64\n","prefixes":["v11","01/21"]}