{"id":2221052,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2221052/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408140635.42546-6-zhiwei_liu@linux.alibaba.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408140635.42546-6-zhiwei_liu@linux.alibaba.com>","date":"2026-04-08T14:06:34","name":"[v5,5/6] target/riscv: Fix smrnmi isa alphabetical order","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"19b20b1555e7255609881f97bc2a335b8a0418b7","submitter":{"id":84720,"url":"http://patchwork.ozlabs.org/api/1.1/people/84720/?format=json","name":"LIU Zhiwei","email":"zhiwei_liu@linux.alibaba.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408140635.42546-6-zhiwei_liu@linux.alibaba.com/mbox/","series":[{"id":499183,"url":"http://patchwork.ozlabs.org/api/1.1/series/499183/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499183","date":"2026-04-08T14:06:34","name":"target/riscv: Implement Smsdid and Smmpt extension","version":5,"mbox":"http://patchwork.ozlabs.org/series/499183/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2221052/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2221052/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default header.b=GF6Edi+6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed;\n d=linux.alibaba.com; s=default;\n t=1775657360; h=From:To:Subject:Date:Message-Id:MIME-Version;\n bh=9+ZwTdMlkH8QNJrGNOxY5TJb3ZzRrMY1qbuZ03Xf7/4=;\n b=GF6Edi+62Vc7x/fP/ueK/cQHPo94SoKT+3Tq6w7gXZVfurRFV1CAy2r2TT41EiWendIL4oar3u7BG+M/y4LokwUbKPxRnjjKMrq6t84SfVw178T4yNCxSurjPTNqae1kWBxN3hLOvrL/PGwUSgJ/BxskbSEaK5pH6S1kLdo9k3Y=","X-Alimail-AntiSpam":"AC=PASS; BC=-1|-1; BR=01201311R471e4; CH=green;\n DM=||false|;\n DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045098064;\n MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0;\n TI=SMTPD_---0X0f.zqR_1775657358;","From":"LIU Zhiwei ","To":"qemu-devel@nongnu.org","Cc":"qemu-riscv@nongnu.org, chao.liu.zevorn@gmail.com, palmer@dabbelt.com,\n alistair23@gmail.com, daniel.barboza@oss.qualcomm.com, liwei1518@gmail.com,\n LIU Zhiwei ,\n Daniel Henrique Barboza ","Subject":"[PATCH v5 5/6] target/riscv: Fix smrnmi isa alphabetical order","Date":"Wed, 8 Apr 2026 22:06:34 +0800","Message-Id":"<20260408140635.42546-6-zhiwei_liu@linux.alibaba.com>","X-Mailer":"git-send-email 2.39.3 (Apple Git-146)","In-Reply-To":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>","References":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=115.124.30.133;\n envelope-from=zhiwei_liu@linux.alibaba.com;\n helo=out30-133.freemail.mail.aliyun.com","X-Spam_score_int":"-174","X-Spam_score":"-17.5","X-Spam_bar":"-----------------","X-Spam_report":"(-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5,\n USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: LIU Zhiwei \nSuggested-by: Daniel Henrique Barboza \nReviewed-by: Daniel Henrique Barboza \n---\n target/riscv/cpu.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)","diff":"diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 8ac935ac06..cb4ccd001d 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -224,9 +224,9 @@ const RISCVIsaExtData isa_edata_arr[] = {\n ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp),\n ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),\n ISA_EXT_DATA_ENTRY(smpmpmt, PRIV_VERSION_1_12_0, ext_smpmpmt),\n- ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),\n ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),\n ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm),\n+ ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),\n ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),\n ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),\n ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg),\n","prefixes":["v5","5/6"]}